# Student Biographies - Virginia Commonwealth University

MOSFETs NMOS Field Effect Transistor MOSFET = Metal Oxide Semiconductor Field Effect Transistor Four terminal device (gate, source, drain, substrate) Unipolar transistor one type of charge carrier FET is a current control mechanism based on an electric field established by the voltage applied to the control terminal Source (S) Gate (G) Drain (D) Metal n+ Oxide (SiO2) Channel region n+ L p-type substrate (Body) Body (B) REP 01/26/20 ENGR224 Page MOSFET 5.1-1 MOSFETs NMOS Cross-section S Metal G W Metal or Polysilicon D Oxide (SiO2) n+ Source

Region L n+ P-type substrate (body) Channel Region B Drain Region REP 01/26/20 ENGR224 Page MOSFET 5.1-2 MOSFETs Creating a Channel for Current Flow + vGS - S Induced n-type channel D G n+ n+ A positive voltage is applied to the gate which forms an inversion layer, or an n-type channel L p-type substrate (Body) B Depletion region REP 01/26/20 ENGR224 Page MOSFET 5.1-3 MOSFETs Operation with Small vDS + vGS

- S iS=iD iG=0 + vDS (small) - iD D G iD(mA) n+ iD n+ 0.4 vGS=Vt+4V 0.3 vGS=Vt+3V 0.2 vGS=Vt+2V Induced n-type channel p-type substrate (Body) B vGS=Vt+1V 0.1 vGS Vt 50 REP 01/26/20 ENGR224 100 150 200 v (mV) DS Page MOSFET 5.1-4

MOSFETs Exercise 5.1 Note that in the small signal linear range, i D is proportional to (vGS-Vt)vDS Find the constant of proportionality for the device below and the range of drain-to-source resistance for vGS=2V to 5V Constant of proportionality iD(mA) point1: 0.4mA 4V(.2V) 0.5mA/V 2 point 1 0.4 vGS=Vt+4V point2 : 0.1mA 1V(.2V) 0.5mA/V 2 0.3 vGS=Vt+3V 0.2 vGS=Vt+2V Drain-to-source resistance v GS Vt 4V : RDS v DS 200mV 2 K iD .1mA point 1 v GS Vt 4V : RDS v 200mV DS 500 iD .4mA 0.1 vGS Vt 50 100 150

200 v (mV) DS Vt=1V REP 01/26/20 ENGR224 vGS=Vt+1V Page MOSFET 5.1-5 MOSFETs Uniform Channel Approximation VS W=width VG>>VD and VS E y x=0 y p-type n+ VD > VS x depletion region edge Assumptions Uniform behavior in the z (channel width) direction The mobility is a constant The x directed electric field is Channel charge approximately a constant within the channel thickness (ych) at a given x. This is known as the gradual channel J n x , y , z q n x, y, z n Ex x , y , z approximation. At a given x, Area The current is constant, independent the y ych z W location of the chosen cross-section (i.e. In x qn x, y , z n E x x dydz independent of x) y 0 z 0

x=L Ex inversion channel n+ Ey REP 01/26/20 ENGR224 Page MOSFET 5.1-6 MOSFETs Charge per unit length in the channel (VGS >> VDS) VGS Gate Electrode (metal) dx v(x) channel source Gate Oxide velocity dx dt drain

v(x) = the voltage at point x Charge dq dv(x)=the incremental voltage about point x dv x E x dx dq x CoxW vGS v x Vt dx ox rSiO2 0 3.9 8.85 x10 Cox tox tox tox REP 01/26/20 ENGR224 14 F cm The voltage drop between the gate and the channel, in excess of the threshold voltage Vt determines the amount of charge Page MOSFET 5.1-7 MOSFETs Derivation of the MOSFET current equation in the Linear Region of Operation dx dv x n E x n dt dx W ych I n n dz qnx , y dy E x x w0 y0 dx dv x n E x n dt dx dq dq x dx dx dv x i velocity n dt dx dt

dt dx dq x CoxW vGS v x Vt dx iD dx nCoxW vGS v x Vt dv x iDS Q 'inversion x vGS=Vt + 3V v DS L i dx C W v D 0 W n ox GS v x Vt dv x 0 2 W vDS iD nCox vGS Vt vDS L 2 Process Layout Geometries Technology REP 01/26/20 ENGR224 Terminal potentials vGS=Vt + 2V vGS=Vt + 1V vGS Vt 200mV Page MOSFET 5.1-8 vDS

MOSFETs Exercise 5.2 Find the expression for rDS=vDS/iD when vDS is small. Find the value of rDS for an NMOS transistor having kn=20mA/V2,Vt=1V, and W/L=100m/10m when operated at vGS=5V 2 W vDS iD k 'n vGS Vt vDS L 2 W for small vDS : iD k 'n vGS Vt vDS L v W rDS DS 1 k 'n vGS Vt L iD REP 01/26/20 ENGR224 vDS 100m 5V 1V 1 20 A V 2 10m iD 1 800 10 6 1.25k rDS rDS Page MOSFET 5.1-9 MOSFETs Operation as vDS is Increased + vGS - S + vDS D G

n+ n+ p-type substrate B REP 01/26/20 ENGR224 Page MOSFET 5.1-10 MOSFETs Channel pinch off Increasing vDS causes the channel to acquire a tapered shape Eventually, as vDS reaches vGS-Vt, the channel is pinched off at the drain end Increasing vDS above vGS-Vt has little effect (theoretically no effect) on the channels shape vDS vGS-Vt Source Channel vDS Drain vDS 0 REP 01/26/20 ENGR224 Page MOSFET 5.1-11 MOSFETs Operation as vDS is Increased (cont.) iD Triode Curve bends because the channel resistance increases with vDS Almost a straight line with slope proportional to (vGS-Vt) vDS vGSVt

Saturation vDS vGSVt Current saturates because the channel is pinched off at the drain end, and vDS no longer affects the channel vGSVt vDSsat vGSVt REP 01/26/20 ENGR224 vDS Page MOSFET 5.1-12 MOSFETs Higher Drain Voltages (pinch-off) For Example VG=3V Vt=1V VS=0 VGS=VG-VS VGS=3V n+ Ey Ey VGD=VG-VD=1V just Vt VDS=VGS-Vt=2V x=0 x=L y Ex inversion channel p-type n+ VD > VS x depletion region edge REP 01/26/20 ENGR224

Page MOSFET 5.1-13 MOSFETs The Saturation Region of Operation 2 W VDS I D C 'ox n VGS Vt VDS L 2 and substitute in VDS VGS Vt 2 W VGS Vt I D C 'ox n VGS Vt VGS Vt L 2 ID 1W 2 C 'ox n VGS Vt 2 L Square Law - REP 01/26/20 ENGR224 i.e The current is proportional to the voltage in excess of the threshold squared Page MOSFET 5.1-14 MOSFETs MOSFET Transistor Operating Regions Summary Linear (triode) Region Pinchoff - onset of Saturation Region

Saturation Region Figure taken from Semiconductor Devices, Physics and Technology, S. M. Sze,1985, John Wiley & Sons REP 01/26/20 ENGR224 Page MOSFET 5.1-15 MOSFETs MOSFET Operation Summary Let: k 'n n Cox Triode Region: vGS >Vt, vDS < vGS-Vt 2 DS W v iD k 'n vGS Vt vDS L 2 Saturation Region: vGS >Vt, vDS vGS-Vt 1 W 2 iD k 'n VGS Vt 1 VVDS 2 L REP 01/26/20 ENGR224 Typical Process-Technology Parameter Values Electron mobility: n 580 cm2/Vs Oxide permittivity: ox =3.97o = 3.97 X 8.85 X 10-14 =3.5 X 10-13 F/cm Oxide Capacitance: Cox =ox/tox = 1.75 fF/m2 for tox=0.02m = 0.35 fF/m2 for tox=0.1m Process transconductance parameter: kn= nCox =ox/tox = 100V2 for tox=0.02m = 20V2 for tox=0.1m Page MOSFET 5.1-16 MOSFETs PMOS Field Effect Transistors Gate (G) Drain (D) Source (S)

Metal p+ Oxide (SiO2) Channel region p+ L n-type substrate (Body) Body (B) REP 01/26/20 ENGR224 Page MOSFET 5.1-17 MOSFETs Sub-threshold Region MOS behavior ID Moderate inversion Small current level < ~1A weak inversion VGS sub-threshold junction leakage 3t I D constant e REP 01/26/20 ENGR224 VDS VGB n0t Bipolar-like behavior In the sub-threshold regime Page MOSFET 5.1-18 MOSFETs CMOS technology REP 01/26/20 ENGR224

Page MOSFET 5.1-19 Figure taken from supplemental material for Digital Integrated Circuits, A Design Perspective, Jan M. Rabaey,1996, Prentice Hall MOSFETs MOSFET Circuit symbols NMOS D D B G PMOS S REP 01/26/20 ENGR224 S G G S S B D G D Page MOSFET 5.1-20 MOSFETs The iD-vDS Characteristics (NMOS) V DS = V + iG=0 vDS + vGS iS=iD -

-V t V GS = 5V Saturation Triode VGS = 4V 1 V GS = 3V - V GS= 2V Square Dependence iD i D (m A ) 2 GS V GS = 1V 0.0 1.0 2.0 v 3.0 DS 4.0 5.0 (V) i D as a function of v DS Figure taken from supplemental material for Digital Integrated Circuits, A Design Perspective, Jan M. Rabaey,1996, Prentice Hall REP 01/26/20 ENGR224 Page MOSFET 5.1-21 MOSFETs iD vs. vGS Characteristic for an NMOS transistor in saturation iDS vDS vGS-Vt

Vt REP 01/26/20 ENGR224 1 W 2 iD k 'n VGS Vt 2 L vGS (V) Page MOSFET 5.1-22 MOSFETs Large Signal Model of a MOSFET in Saturation iG=0 G iD + + 1 W 2 iD k 'n VGS Vt 2 L vGS vDS - S REP 01/26/20 ENGR224 D vGS Vt vDS vGS-Vt Page MOSFET 5.1-23 MOSFETs Finite Output Resistance in Saturation Source Channel Drain

- vDSsat vGS-Vt + - + vDS-vDSsat L L REP 01/26/20 ENGR224 Page MOSFET 5.1-24 MOSFETs Channel Length (Drain Current) Modulation due to changes in VDS VDS VGS Vt triode saturation VA = -(1/) 1 W VGS Vt 2 1 vDS iDS kn' 2 L REP 01/26/20 ENGR224 Page MOSFET 5.1-25 MOSFETs Large Signal Model of the MOSFET Incorporating the Output Resistance iG=0 G iD + vGS D + 1 W 2

iD k 'n VGS Vt 2 L rO vDS - S vGS Vt vDS vGS-Vt V 1 rO A I D ID REP 01/26/20 ENGR224 Page MOSFET 5.1-26 MOSFETs Exercises 5.3 An enhancement mode transistor with V t=2V has its source terminal grounded and a 3V DC source connected to the gate. In which region of operation does the device operate for: a) VD=0.5V VDS = 0.5V < VGS-Vt, in triode region b) VD=1V VDS = 1V = VGS-Vt, in saturation region (pinch-off) c) VD=5V VDS = 5V > VGS-Vt, in saturation region vD + 3V - 5.4 If the transistor above has kn=20A/V2, W=100m and L=10m, find the value of iD in the above cases - ignore the dependence of i D on vDS in saturation. 2 vDS W 0.52 6 100 a) iD k 'n vGS Vt vDS 20 10

3 2 0.5 75AA L 2 10 2 1 W 20 10 6 100 2 3 2 2 100A b) iD k 'n vGS Vt 2 L 2 10 c) iD 100A REP 01/26/20 ENGR224 + Page MOSFET 5.1-27 - MOSFETs Exercises 5.6 An enhancement MOSFET with k n(W/L)=0.2mA/V2, Vt=1.5V, and l=0.02V-1 is operated with vGS=3.5V. Find iD at vDS=2V and vDS=10V. Determine rO at this value of vGS. iDS 1 'W 0.2 10 3 2 3.5 1.5 2 1 0.02 2 0.416mA k n VGS Vt 1 vDS 2 L 2 iDS 1 'W 0.2 10 3 2 3.5 1.5 2 1 0.02 10 0.480mA k n VGS Vt 1 vDS 2 L 2 rO vDS 10V 2V

125k i D 0.480mA 0.416mA REP 01/26/20 ENGR224 Page MOSFET 5.1-28 MOSFETs The iD-vDS Characteristics (PMOS) i D (m A ) V GS = -1V iD V GS = -2V VGS = -3V -1 + iG=0 vDS + vGS iS=iD - V GS = -4V - Saturation -2 Triode V GS = -5V V DS = V -1.0 -2.0 GS -3.0 -4.0 v DS (V) -V t -5.0

0.0 Figure taken from supplemental material for Digital Integrated Circuits, A Design Perspective, Jan M. Rabaey,1996, Prentice Hall REP 01/26/20 ENGR224 Page MOSFET 5.1-29 MOSFETs n-channel Enhancement Mode MOS Transistors Enhancement Mode Transistors. A normally open switch. At zero volts on the gate no current flows ( a positive Voltage must be applied to the gate to enhance a channel of electrons) Source Gate Drain Drain Gate n n p substrate IDS Substrate Source n-channel Source - where electrons come from (-) Drain - where electrons flow to (+) Channel is enhanced (resistive) -VGS REP 01/26/20 ENGR224 Channel is off 0 +VGS Page MOSFET 5.1-30 MOSFETs n-channel Depletion Mode MOS Transistors

Depletion Mode Transistors. A normally closed switch. At zero volts on the gate a current flows ( a negative Voltage must be applied to the gate to deplete the channel of electrons) Source Gate Drain Drain Gate n Substrate n p substrate n-channel Source Source - where electrons come from (-) Drain - where electrons flow to (+) IDS Channel is made stronger Channel is depleted (Off) -VGS REP 01/26/20 ENGR224 0 +VGS Page MOSFET 5.1-31 MOSFETs p-channel Enhancement Mode MOS Transistors Enhancement Mode Transistors. A normally open switch. At zero volts on the gate no current flows ( a negative Voltage must be applied to the gate to enhance a channel of holes) Source Gate Source Drain Gate p

Substrate p n substrate p-channel Drain Source - where holes come from (+) Drain - where holes flow to (-) 0 -VGS +VGS Channel is enhanced IDS REP 01/26/20 ENGR224 Page MOSFET 5.1-32 MOSFETs p-channel Depletion Mode MOS Transistors Depletion Mode Transistors. A normally closed switch. At zero volts on the gate a current flows ( a positive Voltage must be applied to the gate to deplete the channel of electrons) Source Gate Source Drain Gate p Drain p n substrate -VGS Substrate 0 p-channel

Source - where holes come from (+) Drain - where holes flow to (-) +VGS Channel is depleted IDS REP 01/26/20 ENGR224 Page MOSFET 5.1-33 MOSFETs The Body or Back Gating Effect on Threshold Voltage Vbody-Source Slightly (<0.4V) Forward Biased Source (S) Gate (G) n+ Channel region Drain (D) n+ p-type substrate (Body) Gate (G) Source (S) n+ Vbody-Source=0 Channel region Drain (D) n+ p-type substrate (Body) A slight body to source forward bias raises the potential of the electrons in the substrate reducing the gate voltage necessary to invert the surface A reverse body to

source bias lowers the potential of the electrons in the substrate increasing the gate voltage necessary to invert the surface Body (B) Source (S) Vbody-Source Reverse Biased REP 01/26/20 ENGR224 n+ Gate (G) Channel region Vt0 Drain (D) Vt Vt 0 2 f VSB n+ p-type substrate (Body) Vt Gamma Body Effect Parameter 2 qN A Si Cox Page MOSFET 5.1-34 2 f MOSFETs Example 5.1 Design the circuit shown below so that the transistor operates at I D = 0.4 mA and VD= 1V. The

NMOS transistor has Vt = 2 V, nCox = 20 A/V2, L = 10m, and W = 400 m. Assume = 0. V I I V DD D D SS 5V R Since VD = 1V, we are operating in the saturation region. D R V D S 5V REP 01/26/20 ENGR224 1 W 2 C I D 2 n ox L VGS Vt 1 400 VGS 2 2 0.4 20 10 3 2 10 2 2 0 VGS 2 VGS 4VGS 3 0 VGS 3VGS 1 VGS 3 or VGS 1 Choose VGS = 3V. Since gate is grounded, potential at the source

must be -3V. RS VS VSS 3 ( 5) 5k ID 0.4 To establish +1V at the drain, RD V DD V D 5 1 10k ID 0.4 Page MOSFET 5.1-35 MOSFETs Example 5.2 Design the circuit shown below to obtain a current I D = 0.4 mA. Find the value required for R and find the dc voltage VD. Let the NMOS transistor have Vt = 2 V, nCox = 20 A/V2, L = 10m, and W = 100 m. Assume = 0. V DD I D 10V Since VDG = 0V, we are operating in the saturation region. R V D 1 W 2 C I D 2 n ox L VGS Vt 1 100 VGS 2 2 0.4 20 10 3

2 10 2 2 4 VGS 2 VGS 4VGS Choose VGS = 4V since 0V < Vt and VD = 4V. Thus, R VDD VD 10 4 15k ID 0.4 0 VGS 4 VGS 0 VGS 4 or VGS 0 REP 01/26/20 ENGR224 Page MOSFET 5.1-36 MOSFETs Example 5.3 Design the circuit shown below to establish a drain voltage of 0.1V. What is the effective resistance between drain and source at this operating point? Let V t = 1 V, and kn(W/L) = 1 mA/V2. V I DD D The MOSFET is operating in the triode region, since the drain voltage is lower than the gate voltage, and V t is 1V. 5V R Triode, if D V D 0.1V

VDS VGS Vt 1 1 5 1 0 . 1 0.01 0.395 mA ID 2 The required resistor value, RD V DD V D 5 0.1 12.4 k ID 0.395 Effective drain-to-source resistance, r REP 01/26/20 ENGR224 DS VDS 0.1 253 ID 0.395 Page MOSFET 5.1-37 MOSFETs Example 5.4 NMOS

Analyze the following circuit to determine all the node voltages and branch currents, given that Vt=1V and kn(W/L) is 1mA/V2. Neglect the channel length modulation effect (i.e. assume =0) Since the gate current is zero (why?), the voltage at the gate is simply determined by voltage division between RG1 And RG2, and since they are equal VG is VDD/2 or 5 Volts. Since the gate voltage is significantly higher than ground it is likely that the transistor is on, but we don not know if it is in the triode region of operation or in saturation. We will assume that it is saturated and solve the problem and then check the validity of our assumptions (often the hard part for beginners). The saturation equations are easier to work with and that makes a good choice for starting out. If our assumptions do not check out we have to go back and use the triode region equations REP 01/26/20 ENGR224 VDD = +10 V RG1 = 10 M +5 V RG2 = 10 M ID =IS RD = 6 k D G IS =ID assumed S RS = 6 k The drain current has to be equal to the source current since IG is zero VGS = 5 - 6,000(ID)

And in saturation 1 W 2 I D k 'n VGS Vt 2 L Page MOSFET 5.1-38 + vS - MOSFETs Example 5.4 continued Again, in saturation 1 W 2 I D k 'n VGS Vt 2 L VDD = +10 V 1 A 2 I D 0.001 2 5 6,000 I D 1 2 V Which is a quadratic Eq. in ID 18 I D2 25 I D 8 0 This yields two values for ID, 0.89 mA and 0.5 mA Which is valid for our assumption of saturation? For ID of 0.89 mA the source voltage would be 6,000(0.00089) or 5.34 Volts which is higher than the gate voltage and since the gate to source voltage to turn the device on (i.e. threshold voltage) is +1 Volt the device would be off not saturated this answer is not valid. REP 01/26/20 ENGR224 RD = 6 k

RG1 = 10 M +5 V RG2 = 10 M D G assumed S RS = 6 k + vS - For ID of 0.5 mA the source voltage would be 6,000(0.0005) or 3 Volts which means the gate to source voltage is 5-3 or 2 Volts which is greater than the threshold voltage (+1 Volt) and the device is on. But is it saturated? The drain is at 10-(6,000)(0.0005) or 7 Volts VDS=7-3 or 4 Volts Since VDS (4V) is greater than VGS-Vt (2V-1V) the device is by definition in saturation so our initial assumption was correct Page MOSFET 5.1-39 MOSFETs Example 5.5 (PMOS) Design the following circuit so that the transistor operates in saturation with ID=0.5mA and VD=+3V. Let the enhancement type PMOS transistor have Vt=-1V and kp=1mA/V2. Assume = 0. What is the largest value that RD can have while still maintaining saturation-region operation? We were given the conditions to be met so lets start there, ID=0.5mA VDD = +5 V RG1 S G

assumed 1 A 2 D 0.0005 0.001 2 VGS 1 + 2 V RG2 RD vD 2 0.0005 VGS 1 0.001 VGS 1 1 VGS 0, 2V For PMOS VGS Vt VGS is negative VG to ground is VDD -VSG = 5-(2)=+3V The gate voltage can be set by picking appropriate values of RG1 and RG2 in a voltage divider, for example, RG1 = 2M and RG2 = 3M The drain resistor value can be found from V 3 RD D 6k I D 0.0005 REP 01/26/20 ENGR224 =3V The border for saturation to linear occurs at VDS=VGS-Vt so VDSmax=-2-(-1) = -1V, therefore VD to ground max is VDD-VSD=5-(1)=4V At VD=4V and ID=0.5mA, RD=8k Page MOSFET 5.1-40 MOSFETs Example 5.6 (depletion NMOS) The depletion MOSFET in the circuit is required to supply the variable resistor RD with a constant current of 100A. If kn = 20 A/V2 and Vt = -1 V, find the W/L ratio required. Also find the range that R D can have while the current through it remains constant at 100A. Assume l = 0. The MOSFET in this circuit is conducting (V GS = 0). It must be operated in the saturation mode in order to conduct a constant current ID while RD (and VD) is varying.

1 W 2 I D k n VGS Vt 2 L 1 W 2 100 20 0 1 2 L W 10 L The saturated mode of operation will be maintained for VDS VGS Vt 0 1 1, VD 1V REP 01/26/20 ENGR224 VDD = +5 V RD D G + assumed S vD - VD VDD RD I D V VD min 5 1 RD max DD 40k ID 0.1 Thus, RD can vary in range from 0 to 40 k Page MOSFET 5.1-41 MOSFETs Example 5.7 (depletion mode FETs) Design the circuit shown below to establish a dc voltage of +9.9V at the source. At this operating point, what is the effective resistance between the source and the

drain of the transistor? Let Vt = -1V and Kn(W/L) be 1 mA/V2. In this case the gate and the source are just slightly below the drain (0.1V) and VGS=0. VDS is not greater than VGS-Vt (0.1 is not greater than 0-(-1)) so the transistor is in the triode region and the current is 1 2 I D 0.001 0 1 0.1 0.1 2 I D 0.1mA We can now find RS by RS VS 9.9 99k 100k I D 0.0001 VDD = +10 V rDS 1k D G assumed S RS + VS=9.9V - The effective source to drain resistance is V 0.1 rDS DS 1k I D 0.0001 REP 01/26/20 ENGR224 Page MOSFET 5.1-42 MOSFETs Exercise 5.13

Consider the circuit below where the voltage VD1 is applied to the gate of another transistor, Q2. Assume that Q1 and Q2 are identical. Find the drain current and voltage of Q 2. Assume = 0. (see example 5.3) V R 2 10 k Q From example 5.3, VD=4V and ID1=0.4mA. DD V 10V Q1 and Q2 are identical and have equal VGS. R 12.4k D1 2 Q 1 V Assuming that Q2 is also operating in the saturation mode, its drain current will be identical to that of Q1, 0.4mA D1 Thus, V D 2 10 0.4 10 6 V Since VD2 > VG2 (4V), we are indeed operating in the saturation region. REP 01/26/20 ENGR224 Page MOSFET 5.1-43 MOSFETs MOSFET as an Amplifier VDS VGS Vt saturation GS Linear Output

Change IDS-VDS Characteristic VGS=> Linear Input Change VDS does not change output much Since changes in the drain to source voltage does not change the output much we will focus on the IDS-VGS characteristic REP 01/26/20 ENGR224 Page MOSFET 5.1-44 MOSFETs MOSFET Amplifier Configuration We can obtain amplification of a small analog signal by use of an enhancement mode MOSFET. A dc voltage (bias) VGS, is applied along with the input signal to be amplified, v gs superimposed on it. The output voltage is taken at the drain and consists of a dc and ac response. A circuit for amplification is shown below This circuit is not practical because The dc voltage source at the input is difficult to implement Integrated circuit resistors take up too much room MOSFETs are used for loads DD To be used as an amplifier the MOSFET must be biased in the saturation region D To find the dc bias we set the ac component DS of the input to zero and determine the dc D (DC+ac) drain current in saturation (we will neglect + channel length modulation in this case, thatac is we will assume =0) G S gs vDS(t) 1 W 2 V i (t)

I D k 'n VGS Vt 2 L v (t) VGS + DC REP 01/26/20 ENGR224 R (DC+ac) Page MOSFET 5.1-45 MOSFETs The Signal Current at the Drain The dc voltage at the drain, VD will be equal to VDD - RDID To ensure saturation we must have VDS VGS Vt Now we go back to the situation where we have both the dc bias and the ac signal vGS VGS v gs The resulting total instantaneous drain current to be 1 W VGS vgs Vt 2 iDS k n' 2 L 1 W VGS Vt 2 kn' W VGS Vt vgs 1 kn' W vgs 2 iDS k n' 2 L L 2 L dc bias ac response non-linear ac response We can focus on the ac response if we keep the input signal small, such that 1 'W 2 W VGS Vt vgs k n v gs k n'

2 L L REP 01/26/20 ENGR224 or v gs 2VGS Vt Page MOSFET 5.1-46 MOSFETs Transconductance If the small-signal condition specified on the previous page is satisfied we can neglect the last non-linear term in the current equation and express i D as iDS I DS ids Where W VGS Vt vgs id k L ' n And we know that the ratio of id to vgs is the transconductance gm gm id W k n' VGS Vt v gs L In general gm iD vGS REP 01/26/20 ENGR224 vGS VGS Page MOSFET 5.1-47 MOSFETs Voltage Gain

The total instantaneous drain voltage is vD VDD RD iD Using the small signal condition vD VDD RD I D id or vD VD RDid The small-signal component of the drain voltage is vd id RD g m RD v gs The voltage gain is then given by vout vd g m RD vin v gs REP 01/26/20 ENGR224 Page MOSFET 5.1-48 MOSFETs DC Bias with an ac small signal iDS The DC bias level determines the ac parameters By restricting the input signal swing to small values we can linearize the characteristic like we did for amplifier transfer characterisitcs IDS tangent at Q slope g m Bias Point - Q t ids (t) VDD iDS(t) (DC+ac) ac vgs(t) VGS +

DC REP 01/26/20 ENGR224 RD D G S VGS 0 + 0 vGS (V) Vt vgs (t) vDS(t) (DC+ac) - t input Page MOSFET 5.1-49 MOSFETs The Input and Output Signals vGS vgs vGS vD VGS v gs 2 2VGS Vt t vD max VDD to prevent cutoff

gmRD 0 vD min vG max Vt REP 01/26/20 ENGR224 VD t When the gate to source signal is at its maximum the drain current is at its maximum. Maximum drain current means that the drop across the drain resistor is at its maximum or that the drain to source voltage of the MOSFET is at its minimum The output is therefore 180 degrees out of phase from the input. We have an inverting small signal amplifier in this configuration In order for the transistor to operate in the saturation region at all times there is a minimum drain voltage that must be maintained. The input signal must be small enough to keep the output above the minimum vout vd g m RD vin v gs Page MOSFET 5.1-50 MOSFETs Small-Signal Saturation Equivalent Circuit Models G + gmvgs vgs - D S

ro VA ID G D + gmvgs vgs - ro From a small-signal point of view the FET behaves like a voltage controlled current source as shown on the top figure to the left. Th input resistance is high (ideally infinite) After the DC analysis is done to determine the ac parameters and then the ac equivalent circuit is drawn. A DC voltage source is ideally immune to changes in current so small ac voltage changes do not cause change in current (dI/dV is zero or R is zero) it is replaced by a SHORT circuit. Current source are replaced by OPEN circuits In the first model is was assumed that the drain current did not change with increasing VDS in saturation but we know that it does. The dependence can be modeled by a finite resistance ro, between source and drain, whose value is approximated by the equation shown at the left. S REP 01/26/20 ENGR224 Page MOSFET 5.1-51 MOSFETs Applying the small-signal model On the previous page VA = 1/ . Which we can determine from the Id-Vd characteristic,

typically in the 10k to 1,000k range Remember, the ac parameters, gm and ro depend on the DC bias point The gain for the following circuit is given below (note that ro reduces the gain) vd g m RD || ro v gs VDD iDS(t) (DC+ac) ac vgs(t) VGS + RD D G DC ac small-signal circuit S G + vDS(t) vgs D + vgs(t) - gmvgs ro RD - (DC+ac) REP 01/26/20 ENGR224 Page MOSFET 5.1-52

+ vds - MOSFETs The Transconductance - gm The transconductance as we have seen already is the incremental change in drain current due to an incremental change in gate voltage or W g m k n' VGS Vt L saturation current equation for If we solve the The transconductance of a bipolar transistor is proportional to the bias current (not the square root of it) and does not depend on the physical size or geometry We can write gm in another useful way, as shown VGS-Vt we get VGS Vt 2 I D W k n' and by substitution L ' W k n' L W 2I D 2 VGS Vt So is proportional to g mgm

2k n I Dthe square root of the dc bias current L At any bias current gm is proportional to the square root of W/L REP 01/26/20 ENGR224 2I D ID gm VGS Vt 1 V V GS t 2 for Veff VGS Vt 1 ID which we can compare to 2 V Vt is ~25mV eff but gm IC gm BJT and transisto rs power MOSFETs arefor smaller use less VT 1 VGS Vt ~ 100mV 2 Page MOSFET 5.1-53 MOSFETs Example 5.8 - Complete Amplifier Analysis In the following circuit, a discrete MOSFET amplifier is shown in which the input signal vi is coupled to the gate via a large capacitor, and the output signal at the drain is coupled to the load resistance RL via another large capacitor. We will assume that the coupling capacitors are large enough so that they act as short circuits for the ac signal frequencies

of interest. We wish to analyze the amplifier circuit to determine its small-signal voltage gain and its input resistance. The transistor has V t=1.5V, kn(W/L) = 0.25mA/V2, and VA = 50V. Start by doing the dc analysis DD V =15V 1 0.00025VGS 1.5 2 2 VD since I G 0 ID VGS RD=10k RG=10M D 1 2 I D 0.00025VGS 1.5 2 2 I D 0.000125VD 1.5 ac Rin + vi - G S + vDS(t) RL=10k VD 15 RD I D 15 10,000 I D VD 4.4V I D 1.06mA REP 01/26/20 ENGR224

The other solution is not valid (contradictory) Page MOSFET 5.1-54 MOSFETs ac equivalent circuit for Example 5.8 VDD=15V RG=10M RD=10k D ac Rin + vi G + S vDS(t) - VDD is shorted to ground in the ac circuit RL=10k - RG G + vgs - vi ac small-signal equivalent circuit D + vgs - gmvgs ro

RD RL + vo - Rin REP 01/26/20 ENGR224 Page MOSFET 5.1-55 MOSFETs ac analysis for Example 5.8 The value of gm is given by W g m k n' VGS Vt L g m 0.00025 4.4 1.5 0.725 Av mA V The MOSFET output resistance ro is V 50 ro A 47k I D 0.00106 The value of the voltage gain Av is given by vo g m RD || RL || ro vi Av 0.00072510,000 || 10,000 || 47 Av 3.3 V V We can now us the ac equivalent circuit to determine the expression for the output voltage in terms of the gate to source small-signal voltage vo g m v gs RD || RL || ro

v gs vi Since RG is so large REP 01/26/20 ENGR224 Page MOSFET 5.1-56 MOSFETs Evaluation of the Input Resistance for Example 5.8 To find the input resistance we note that the input current is given by ii vi vo vi Rin RG vo vi 4.3vi 1- 1- 3.3 RG vi RG RG vi RG 10,000,000 2.33M ii 4.3 4.3 REP 01/26/20 ENGR224 Page MOSFET 5.1-57 MOSFETs The Source Absorption Theorem (Appendix E) Used to derive the T Model for a MOSFET I1 Node 1 I2 Y Node 2 I1 Y V1 V2 I1 YV1 1 V2 V1 V1

V2 KV1 I1 YV1 1 K Y1V1 I1 Y1 Y 1 K I 2 Y V2 V1 I 2 YV2 1 V1 V2 I 2 Y 1 1 K V2 Y2V2 I 2 Node 1 V1 I1 I2 Node 2 Y1 Y2 V2 KV1 Y2 Y 1 1 K REP 01/26/20 ENGR224 Page MOSFET 5.1-58 MOSFETs The T Equivalent Circuit Model ig = 0 G G + gmvgs vgs -

S S G id ig = 0 G ig = 0 gmvgs + 1 gm vgs S X + ro gmvgs gmvgs vgs - D D id D is X + id gmvgs gmvgs vgs S

D is is REP 01/26/20 ENGR224 Page MOSFET 5.1-59 MOSFETs Modeling the Body Effect The body effect (or back gate effect) occurs when the source is NOT at the same potential as the substrate (body). The substrate acts as a second gate and therefore we include a second dependent current source in our model, as shown below g mb iD vBS the dependence is linked to the threshold voltage D vGS constant, v DS constant g mb g m Vt VSB 2 2 f VSB G G 0 .1 0 .3 S D + gmvgs vgs - ro gmbvbs vbs + B

S REP 01/26/20 ENGR224 Page MOSFET 5.1-60 MOSFETs Exercise 5.17 For the following amplifier, let VDD = 5V, RD = 10k, Vt = 1 V, kn = 20 A/V2, W/L = 20, VGS = 2V and = 0. Find the dc current ID and the dc voltage VD Find gm find the voltage gain If vgs = 0.2sint volts, find vd assuming that the small-signal approximation holds. What are the maximum and minimum values of vD. Use the following equation to find the various components of the drain current 1 W VGS Vt 2 kn' W VGS Vt vgs 1 kn' W vgs 2 iDS k n' 2 L L 2 L VDD iDS(t) (DC+ac) ac vgs(t) VGS + DC REP 01/26/20 ENGR224 RD D G S + vDS(t) (DC+ac)

Page MOSFET 5.1-61 MOSFETs Exercise 5.17 continued Using the following identity show that there is a slight shift in ID (by how much?) and that there is a second harmonic component (2nd harmonic has a frequency of 2) Express the amplitude of the second harmonic component as a percentage of the amplitude of the fundamental (this is known as the second-harmonic distortion) 1 1 sin 2 t cos 2t 2 2 REP 01/26/20 ENGR224 Page MOSFET 5.1-62 MOSFETs Biasing MOSFET Amplifier Circuits Biasing is the establishment of an appropriate dc operating point for the transistor. An appropriate dc bias point has a stable and predictable dc drain current ID, and a dc drain to source voltage that ensures operation in the saturation mode for all expected input signal levels. VDS VGS Vt saturation GS Linear Output Change IDS-VDS Characteristic VGS=> Linear Input Change VDS does not change output much Discrete component MOSFET circuits are not common but we will use them to introduce various biasing techniques. REP 01/26/20 ENGR224 Page MOSFET 5.1-63 MOSFETs MOSFET Biasing - Single Supply

Plus side of MOSFET bias circuit design - the gate current is zero (easier to design) Negative side of MOSFET bias circuit design - V t (VGS response) varies more than vBE does in BJT circuits. The circuit shown at the right is commonly used when a single power supply is available. A voltage divider is used to establish a fixed dc voltage at the gate. Since the gate current is zero the two gate bias resistors RG1 and RG2 can be selected to be very large (M range) This will provide a large amplifier input resistance A resistor, called a self bias resistor is connected to the source. If the device is turned on more (more source current) the drop across source resistor will increase and reduce the current. A balance (negative feedback) situation will be created. RD is selected to be as high as possible to obtain high gain but small enough to allow for a large enough output signal swing at the drain while still keeping the MOSFET in saturation at all times. REP 01/26/20 ENGR224 V R G1 DD R I D D R G2 R Page MOSFET 5.1-64 S MOSFETs MOSFET Biasing - Dual Supplies For symmetric supplies (positive and negative of the same

magnitude) a simpler bias arrangement can be used. The resistor RG establishes a dc ground at the gate of the transistor. Directly grounding the gate will also establish a dc bias but R G is used to increase the input resistance seen by a signal source that may be capacitively coupled to the gate RD is selected to be as high as possible to obtain high gain but small enough to allow for a large enough output signal swing at the drain while still keeping the MOSFET in saturation at all times. V DD R I D R R G V SS REP 01/26/20 ENGR224 D Page MOSFET 5.1-65 S MOSFETs MOSFET Biasing with a Constant Current Source Having a constant current source establishes the source and drain current level. We will look at how to construct a constant current source shortly As before RD is selected to be as high as possible to obtain high gain but small enough to allow for a large enough output signal swing at the drain while still keeping the MOSFET in saturation at all times. As before, The resistor RG establishes a dc ground at the gate of the transistor. Directly grounding the gate will also establish a dc bias but R G is used to increase the input resistance seen by a signal source that may be capacitively coupled to the gate

R I D R I G V SS REP 01/26/20 ENGR224 D Page MOSFET 5.1-66 MOSFETs Common-Source Circuit with Resistive Gate Feedback The feedback resistor RG forces the dc voltage at the gate to be the same as that of the drain (since IG = 0). The input can be capacitively coupled to the gate and the output can be taken at the drain to form a simple common-source amplifier. The output signal swing is limited on the low side since the drain (which is tied to the gate) must be high enough to satisfy the threshold voltage gate to source. If the output goes too low the transistor slips out of saturation into the triode region of operation and the output will be distorted. As before RD is selected to be as high as possible to obtain high gain but small enough to allow for a large enough output signal swing at the drain while still keeping the MOSFET in saturation at all times. REP 01/26/20 ENGR224 V 0 R DD R D G

Page MOSFET 5.1-67 I D MOSFETs Biasing of Discrete MOSFET Amplifiers Four circuits for biasing the MOSFET in discrete-circuit design. V R G1 V R I D D G2 R R R G S V SS classical arrangement 2 power supplies REP 01/26/20 ENGR224 R D 0 R DD D D

D R R I DD R I V DD R G I G D I D S V SS constant current source common-source circuit Page MOSFET 5.1-68 MOSFETs Biasing of Discrete MOSFET Amplifiers Exercise 5.22 Design the circuit below for a MOSFET having k n(W/L) = 0.5 mA/V2 and Vt = 2V, and utilizing two power supplies, 10V. Design for ID = 1mA and allow for a signal swing at the drain of 2V. The amplifier is required to present a 1M input resistance to a signal source that is capacitively coupled to the gate. Assume =0. 10V W k 'n 0.5mA/V2 and Vt 2V L RG 1M, I D 1mA R I

Thus, 1 2 1 0.5VGS 2 2 VGS 4V D D 1M R G R S VG 0, VS 4V RS 4 10 6k .001 Where we have neglected the signal component of VG VD min VG Vt 0 2 2V REP 01/26/20 ENGR224 10V To allow for a 2V signal swing at the drain, 10 0 VD 0V, thus RD 10k .001 Page MOSFET 5.1-69 MOSFETs Design Philosophy The circuits that we have just looked at are not suitable for integrated circuit design. They use too many resistors which take up room and are therefore expensive. It turns out that since we are making small MOSFETs anyways, that if we can use transistors that act sort of like resistors we can make much smaller (more dense) circuits.

O 1 W 2 I D1 k ' n VGS Vt 2 L 1 V VGS I D1 I REF DD R I 2 GS - constant current source I O I D2 IO I REF REP 01/26/20 ENGR224 REF I I D1 Q 1 For Q2, 1 W 2 k ' n VGS Vt 2 L 2 W L 2 W L 1 DD V

GS - current mirror Page MOSFET 5.1-71 Q O 2 V O _ MOSFETs Effect of VO on IO In the previous current source description we assumed that the transistor Q2 is operting in saturation IO Slope VO VGS Vt 1 rO RO I REF VO V rO 2 A 2 I O IO Region of constant current operation VGS Vt VGS REP 01/26/20 ENGR224 VO Page MOSFET 5.1-72

MOSFETs Example 5.9 Given VDD=5V and using IREF=100A, it is required to design the circuit shown below to obtain an output current whose nominal value is 100A. Find R if Q1 and Q2 are matched, have channel lengths of 10m and channel widths of 100m, Vt=1V and kn=20A/V2. What is the lowest possible value of VO? Assuming the fabrication technology results in an Early voltage that can be expressed as V A=10L, where L is in microns and VA in volts, find the output resistance of the current source. Also find the change in output current resulting from a 3V change in VO. VGS 2V V I R REF I I 0 D1 Q 1 5 2 R 30k 100 A VO min VGS Vt 2 1 1V DD V Since L=10m, V 0 0 O Q O 2

GS - 1 100 I D1 I REF 100 20 VGS 1 2 2 10 REP 01/26/20 ENGR224 V A 10 10 100V 100V rO 1M 100 A The output current will be 100A at VO=VGS=2V. If VO changes by +3V, the corresponding change in IO will be 3%, I O VO 3V 3A rO 1M Page MOSFET 5.1-73 MOSFETs Current-Steering Circuits V I 2 I REF DD V I REF I V DD Q R I

2 4 I I D1 Q 1 V Q 2 Q 3 Q threshold voltage for n-channel devices 5 I 5 I 4 3 W L 5 , W L 4 where I 4 I 3 V D 5 VDD VGS 5 Vtp GS 1 - REP 01/26/20 ENGR224 V SS W L 3 W L 1 5 I 4

and I 3 I REF VD 2 , VD 3 VSS VGS1 Vtn GS 5 - W L 2 W L 1 threshold voltage for p-channel devices Page MOSFET 5.1-74 MOSFETs Basic Configurations of Single-Stage IC MOS Amplifiers V V DD v I I v v V DD v O DD I v O I v REP 01/26/20 ENGR224 I V SS Page MOSFET 5.1-75

O MOSFETs Resistive Load Common Source Amplifier An ideal current source has an infinite resistance, the current does not depend on the voltage at the node to which it is connected, but what happens if we use a resistive load The resistor constrains the current flow through the transistor and vice-versa. For the solid resistor load curve plotted on the transistor characteristic shown below the resistance is less than that of the dashed curve. On the solid curve the valid operating points (curve intersections) are labeled with a letter and on the dashed curve the letters have a prime On the next page we plot the voltage transfer characteristic of this amplifier V DD R Vtn 0.8V v G I D iD1 + VR - v Q1 in triode D O I REF S Load curve Q1 in saturation vGS1 4V VID vGS 1 3V VIC C B

vGS1 2V VIB A D vGS1 1V VIA Vtn 0.8V A 0 common-source VR=VDD-VDS REP 01/26/20 ENGR224 1 2 Vout 3 4 5V VDD Vin vDS 1 vO Page MOSFET 5.1-76 MOSFETs Resistive Load Common Source Amplifier continued The plot of the transfer characteristic of the common-source amplifier with a resistive load is shown below Since the resistor is not an ideal current source the gain varies with the load resistance The higher the load resistance the higher the gain but the smaller the allowed input signal swing (an still have the transistor saturated) VDD 5 saturation A 4 R1>R2 3

Vout 2 gain is proportional to the slope Gain1>Gain2 B A 1 B C C 0 0 Vtn 1 REP 01/26/20 ENGR224 2 3 D triode D 4 5 Vin Page MOSFET 5.1-77 MOSFETs The CMOS Common-Source Amplifier (PMOS current source load) If the PMOS active load device is made with a long channel then lambda is small (the magnitude of V A is large or the transistor output resistance ro is large). In other words a long channel load acts more like an ideal current source. rO 2 V I I REF

DD V SG - 3 Q 2 v v 1 rO 2 one curve not a family of curves O Q 1 CMOS common-source amplifier circuit REP 01/26/20 ENGR224 Slope v SG VSG - REF v Q2 in saturation I REF i + I - Q2 in triode i

Q VA2 0 V SG Vtp VSG v i-v characteristic of the active-load Q2 Page MOSFET 5.1-78 MOSFETs Graphical construction to determine transfer characteristic We expect to have a transfer characteristic that has a high gain since output resistance of the load transistor can be made high (long channel) The load curve is like a high value resistor that has been translated upwards We are most interested in the area of intersection between A and B for amplification iD1 Q1 in saturation Q1 in triode Load curve vGS1 V1B B A I REF 0 VOB VDD VSG vGS1 V1 A

VDD VDD VSG Vtp REP 01/26/20 ENGR224 vDS1 vO Page MOSFET 5.1-79 MOSFETs Transfer Characteristic of the active load common source amplifier When the input is low the load transistor is in the triode region, as the input voltage is increased the active load becomes saturated. The gain is relatively high and depends on the output resistance of the transistor used in the current mirror VDD I VDD VSG Vtp II III IV I A II III IV Q1 Q1 Cutoff Saturation Q2 Triode Q1

Saturation Q2 Saturation Q1 Triode Q2 Saturation B VOB Vtn V1 A REP 01/26/20 ENGR224 V1B Page MOSFET 5.1-80 MOSFETs Small-signal equivalent circuit of the common-source config. D1,D2 vi + - v gs1 g m1v gs1 ro1 ro 2 v o - vo AV g m1 ro1 ro 2

vi S1,S2 Since ro1 and ro2 are usually large the gain can be large without taking up a lot of room on the chip with an integrated resistor. If we use physically based parameters for the transistors we get a design equation in terms of the transistors length, width, transconductance, output resistance and reference current source value Voltage gains on the order of 20-100 are obtained using CMOS common-source configuration The source of each device is connected to the body so the body effect on the threshold voltage is not a factor REP 01/26/20 ENGR224 W g m1 2k 'n I REF L 1 The gain then becomes W 2k 'n L 1 Av 1 1 V A1 VA 2 1 I REF If we assume that VA1 V A2 AV 1 W VA k 'n 2 L 1 I REF Page MOSFET 5.1-81 ro1 VA1 I REF MOSFETs Effect of RS on AC gain In section 5.6 we discussed various DC biasing schemes and in those schemes we saw that the source resistor, RS (like its counterpart RE in the BJT case) provides negative feedback to the gate to source voltage and helps to stabilize the DC value of ID. If the DC bias point of the gate is increased the source current will increase but not by as much as when there is no source resistance This source resistance DOES affect the AC gain!

Consider the case of a MOSFET biased to have a g m of 30mA/V, rO=16K, and RD=470 AC model WITHOUT RS: G vi vo vi V D + vgs(t) - gmvgs ro RD R + vo - g m RD rO 30 X 10 3 (470 16 K) 13.7 V REP 01/26/20 ENGR224 DD v G I + V D -RD D v O S

RS V common-source with a source resistance Page MOSFET 5.1-82 MOSFETs Effect of RS on AC gain (cont.) G vi Now consider AC gain WITH RS, let RS=10: More easily analyzed with the T model: D D + vgs(t) - gmvgs ro RD + vo - + G + 1 gm v gs vi 1 g RS m v 33.33 0.7692v i i 33.33 10 vi

vgs S gmvgs 1 gm RS vO g m vgs RD rO 30 X 10 3 0.7692vi (470 16 K) 10.54vi vo vi 10.54V REP 01/26/20 ENGR224 V Page MOSFET 5.1-83 ro RD vo - MOSFETs The use of a Source By-Pass Capacitor In the circuit shown on this page, at low frequencies, the source capacitor CS is an open circuit and the source resistance has a voltage drop across it which reduces the gate to source voltage across the transistor. On the next page the ac equivalent circuit is shown V DD RD v G I ZS D + VRD

- v O S RS CS common-source with a source resistance REP 01/26/20 ENGR224 Page MOSFET 5.1-84 MOSFETs The use of a Source By-Pass Capacitor (ac circuit) vi + - v g m v gs gs - RD v o S1 ZS RS REP 01/26/20 ENGR224 CS Z Cs 1 j C

as Z Cs 0 CS short circuit (high frequencies) CS open circuit (low frequencies) Note that Vgs does not equal vi now Page MOSFET 5.1-85 MOSFETs The CMOS Common-Gate Amplifier In this case a constant dc level is applied to the gate of the transistor and the input signal is applied to the source The signal source at the gate will be zero (hence the name common gate) There will be a potential difference between the source and the bulk (body) so we need to use the model which includes that effect. V DD Q I V SG - 3 Q v REF v O Q v I g m1v gs1 gs1

g mb1vbs1 - 1 BIAS D1,D2 i v G1 2 vi +- ro1 + S1 - v bs1 B1 - common-gate amplifier vi=VSG vo=VDG REP 01/26/20 ENGR224 Body effect Ri Vgs1=-vi vbs1=-vi small-signal equivalent circuit Page MOSFET 5.1-86 v ro 2

o - MOSFETs Simplified circuit vi vo ro1 ro1 ii vi D1,D2 S1 + - g m1 g mb1 vi ro 2 v o - Ri output node equation vi vo v g m1 g mb1 vi o ro1 ro 2 vo 1 g m1 g mb1 ro1 // ro 2 vi ro1 Av g m1 g mb1 ro1 // ro 2 Av if 1/ro1<

ii g m1 g mb1 vi Ri vi vo ro1 ro 2 vi 1 1 ii g m1 g mb1 ro 2 The body effect adds to the gain but reduces the input resistance The active load (ro2) reduces the gain but slightly increases the input resistance By comparison the Common-Gate configuration has a gain similar to that of the common-source amplifier but the input resistance is much lower The common-gate configuration is used in a combination circuit called a cascode amplifier that we will study later in EGRE307. REP 01/26/20 ENGR224 Page MOSFET 5.1-87 MOSFETs The Common-Drain or Source-Follower Configuration V V I DD v REF DD i Q 5 v Q Q 3 The common-drain or source follower configuration is used as buffer amplifier. Although its voltage gain is less than unity it has a low output resistance and is

therefore capable of driving low impedance loads with little loss of gain. Typically found in the output stage of a multi-stage amplifier. The fact that its impedance is buffered can be used to extend the high-frequency response range of amplifiers and speed up digital circuits. Vdd is at signal ground hence the name common drain The input impedance is very high since it is the gate of a MOSFET (THIS IS A VERY BIG ADVANTAGE OVER BJTs) G1 o v 2 vi V SS common-drain or source-follower D1 + - g m1v gs1 gs1 g mb1vbs1 S1 ro1 + ro 2 v o - v bs1 B1 Signal Ground -

small-signal equivalent circuit (again the body effect is included) Use the source absorption theorem to transform the dependent source into a resistance 1/g mb1 REP 01/26/20 ENGR224 Page MOSFET 5.1-88 MOSFETs Simplified circuit G1 vo vs1 g m1 RS v gs1 vi v gs1 vs1 v gs1 g m1 RS v gs1 v vi + - S1 vi 1 g m1 RS v gs1 g m1v gs1 gs1 RS v o - RS 1 g mb1 Av // ro1 // ro 2 The body effect reduces the gain by ~10 to 30 percent Av Av vo g R m1 S

vi 1 g m1 RS g m1 1 1 g m1 g mb 2 ro1 ro 2 g m1 , g m1 g mb1 g mb1 g m1 1 Av 1 typically 0.1<<0.3 REP 01/26/20 ENGR224 0 Page MOSFET 5.1-89 MOSFETs NMOS Load Devices - Saturated Enhancement Mode VDD Saturated Enhancement Mode Load VGS=VDS therefore always saturated locus of points on many curves i + D i i D2 VGS=VDS G2 G S - G1 VGS1=Vin 0 V t

1 W 2 i k 'n v Vt , v Vt 2 L VDS2 - S2 v + D1 + VDS1=Vout S1 - v VGS2=VDS2 i x x x 0 REP 01/26/20 ENGR224 VDD Vt 2 VDD Page MOSFET 5.1-90 MOSFETs NMOS Amplifier with Enhancement Load V iD1 DD Q Q 2 v A O I V3 V1

0 - vO II Q1 in saturation III Q1 in triode region B V3 0 Vt1 REP 01/26/20 ENGR224 vDS1 A L 1 L2 L 1 1 L2 1 2 Due to the body effect on Vt VSB for Q2 is not equal to zero (reduces the gain) vGS 1 Vt1 I Q1 cutoff V1 Av W L 1 W L 1 V v W L 2 t W L 2 I VDD Vt 2 VDD VDD Vt 2 vO VDD Vt

W W W W vGS 1 ... Av vGS 1 V B 2 iD 2 iD1 v Load curve V vI Page MOSFET 5.1-91 MOSFETs NMOS Amplifier with Enhancement Load Positives Uses the same type of device for the load as the driver (enhancement) Negatives Lower Gain than the Depletion Mode Load Smaller output signal swing (The output does not go all the way up to V DD) REP 01/26/20 ENGR224 Page MOSFET 5.1-92 MOSFETs NMOS Load Devices - Saturated Depletion Mode DepletionMode Load, VGS=0 Always on IDS i Depletion Mode Load VGS=0 Always on

D G VGS i 0 REP 01/26/20 ENGR224 triode + v S - In saturation 1 W v i k 'n V 2 tD 1 2 L VA v i I DSS 1 VA 1 W I DSS k 'n V 2 tD 2 L saturation Slope 1 W I DSS k 'n V 2 tD 2 L V tD v Page MOSFET 5.1-93 1 rO 2 MOSFETs NMOS Amplifier with Depletion Load V

Q DD G1 2 D1,G2.S2 vi iD v Q 1 I v + - v gs1 g m1v gs1 - O g mb 2 vbs 2 ro 2 D2,B2 S1,B1 - ro1 - Av 1

vO // ro1 // ro 2 g m1 vI g mb1 Av Av REP 01/26/20 ENGR224 g m1 g m1 g mb 2 g m 2 W L 1 W L 2 1 Page MOSFET 5.1-94 v o - MOSFETs NMOS Amplifier with Depletion Load vO Load curve iD1 vGS1 ... C B vGS 1 ... VDD I II III IV A VDD VtD

B A V 0 DD Positives VtD VDD vO VOB Higher Gain than the Saturated Enhancement Mode Load Larger output signal swing (all the way up to VDD) Negatives Requires a different type of device (depletion) for the load and is therefore more complicated REP 01/26/20 ENGR224 C VtE I Q1 Q2 Off Triode II Q1 Q2 Saturation Triode vI Q1 Saturation III Q2 Saturation Triode IV Q1 Q2 Saturation Page MOSFET 5.1-95 MOSFETs The CMOS Digital Logic Inverter

For any IC technology used in digital circuit design, the basic circuit element is the logic inverter. The inverter uses two matched enhancement-type MOSFETS; an n-channel and a pchannel. The body of each device is connected to its source which eliminates any body effect. V Q v V DD Q P v I Q N CMOS inverter REP 01/26/20 ENGR224 DD O v P i i v Q DP I DN O N simplified inverter circuit Page MOSFET 5.1-96 MOSFETs Circuit Operation

We assume that the n-channel device is the driver, and the p-channel device is the load. When the input is high, vO=VOL=0 Volts, and the power dissipation in the inverter is 0. V DD v V SGP 0 - DD Q i v SGN DD P i v Q V vGSN VOH VDD Operating point O 0 N VOL 0 Load curve r

vSGP 0 VDD VDD v O 0 DSN vO W rDS 1 k 'n VDD Vtn L n - Operation of the CMOS inverter when vI is high REP 01/26/20 ENGR224 Page MOSFET 5.1-97 MOSFETs Circuit Operation, contd We assume that the n-channel device is the driver, and the p-channel device is the load. When the input is low, vO=VDD, and the power dissipation in the inverter is 0. V DD Load curve vSGP VDD - Q i v SGN v Q vGSN VOL 0

O 0 N DD r P i V vGSP VDD VOL 0 DSP v Operating point VOH VDD VDD 0 O VDL vO W rDSP 1 k ' p VDD Vtp L p - Operation of the CMOS inverter when vI is low REP 01/26/20 ENGR224 Page MOSFET 5.1-98 MOSFETs Circuit Operation, contd The basic CMOS logic inverter behaves as an ideal inverter

The output voltage levels are 0 and V DD, and the signal swing is the maximum possible. This results in wide noise margins. The static power dissipation in the inverter is 0 A low-resistance path exists between the output terminal and ground (in the lowoutput state) or VDD (in the high-output state). The low output resistance makes the inverter less sensitive to the effects of noise and other disturbances. The active pull-up and pull-down devices provide the inverter with high outputdriving capability in both directions. The input resistance of the inverter is infinite (because I G=0). Thus the inverter can drive an arbitrarily large number of similar inverters with no loss in signal level. REP 01/26/20 ENGR224 Page MOSFET 5.1-99 MOSFETs Voltage Transfer Characteristic PMOS Load Lines IDn V in = V DD -V GSp IDn = - I Dp V out = V DD -V DSp Vout IDp Vin=0 IDn IDn Vin=3 VGSp=-2 V DSp Vin=0 Vin=3 VDSp Vout VGSp=-5 Vin = V DD-V GSp IDn = - IDp REP 01/26/20 ENGR224 Vout = V DD-V DSp Page MOSFET 5.1-100 Figure taken from supplemental material for Digital Integrated Circuits, A Design Perspective, Jan M. Rabaey,1996, Prentice Hall MOSFETs CMOS Inverter Load Characteristics

In,p V in = 0 Vin = 5 NMOS PMOS Vin = 4 Vin = 1 Vin = 4 Vin = 3 Vin = 2 Vin = 3 Vin = 4 V in = 3 Vin = 2 Vin = 2 Vin = 1 Vin = 0 Vin = 5 REP 01/26/20 ENGR224 Page MOSFET 5.1-101 Figure taken from supplemental material for Digital Integrated Circuits, A Design Perspective, Jan M. Rabaey,1996, Prentice Hall MOSFETs The Voltage Transfer Characteristic For QN, 1 W iDN k 'n vI Vtn vO v 2 O for vO vI Vtn 2 L n and 1 W 2 iDN k 'n vI Vtn for vO vI Vtn 2 L n For QP, 1 W 2

iDP k ' p VDD vI Vtp VDD vO VDD vO for vO vI Vtp 2 L p and 1 W iDP k ' p VDD vI Vtp 2 L p Wp Wn n p REP 01/26/20 ENGR224 2 for vO vI Vtp W W k 'n k ' p L n L p Page MOSFET 5.1-102 MOSFETs The Voltage Transfer Characteristic, contd QN in saturation QP in triode vO QN off VOH V DD Slope = -1 A NM H VOH VIH

V DD Vt 2 B VDD Vt 2 C VOL 0 REP 01/26/20 ENGR224 NM L VIL VOL QN in saturation QP in saturation Slope = -1 QP in saturation QN in triode QP off D 0 Vt VIL VIH V V V DD t DD V Vth DD 2 vI Page MOSFET 5.1-103 MOSFETs The Complementary MOS (CMOS) Inverter Complementary means +5 V both nMOS and pMOS

transistors are used source of holes A polite tug OWar! gate p channel (n well) Only one device pulls at a drain for holes time Vin Vout A High Voltage on drain for electrons Vin turns On the n channel (p wafer) NMOS device and gate source of electrons turns Off the PMOS device A Low Voltage on Vin The source is where charge turns off the NMOS carriers come from and the and turns On the drain is where they flow to, PMOS holes come from the higher Power is dissipated voltage and flow towards a only when the output more negative terminal, is switching from low electrons come from the more to high or high to low negative terminal and flow towards the positive REP 01/26/20 ENGR224 Vgsp= Vgp-Vsp = 5-5 = 0 g=5 +5 V s=5 open Vin = + 5V Vout = 0 V closed g=5 s=0 Vgsn= Vgn-Vsn = 5-0 = 5

+5 V Vgsp= Vgp-Vsp = 0-5 = -5 s=5 g=0 closed Vin = 0 Vgsn= Vgn-Vsn = 0-0 = 0 g=0 Vout = + 5V open s=0 Page MOSFET 5.1-104 MOSFETs How are Noise Margins Determined? The slope of the voltage transfer characteristic of an inverter is the gain. There are three key points on the gain plot The point at which the magnitude of the gain is first equal to unity (45 degrees) The point at which the magnitude is maximum The point second point at which the gain is again equal to unity VOH |slope| = 1 5 |slope| = Maximum = 5 4 VOUT 3 (Volts) 2 VOL |slope| = 1 1 0

|gain| slope 1 VIL 2 3 VIH 4 5 VIN (Volts) max 5 1 REP 01/26/20 ENGR224 VIN (Volts) Page MOSFET 5.1-105 MOSFETs What Noise Margins really mean On the previous page VIL was equal to 1.2V and VIH was equal to 3V VOL was equal to 0.7V and VOH was equal to 4.9V The Noise Margins are defined as follows NML = VIL - VOL NMH = VOL - VIL in our case = 1.2 - 0.7 = 0.5 Volts = 4.9 - 3.0 = 1.9 Volts VOH 5 VOUT 4 3 (Volts) 2 VOL 1 0 |slope| = 1 |slope| = Maximum = 5

|slope| = 1 1 2 3 4 VIL VIH 5 VIN (Volts) What the output What the input produces accepts solid high +5V High VOH = (5- 4.9) V Marginal High VIH = 3V NMH = (5-3)-(5-4.9) solid and up =1.9V signals Marginal Low VIL = 1.2V Low VOL = NML = 1.2-9.7=0.5V solid low (0.7- 0) V 0V REP 01/26/20 ENGR224 Page MOSFET 5.1-106 MOSFETs How does an Inverter (with gain) restore a poor signal level? Assume that we have two identical inverters in series and that they both have the same voltage transfer characteristic given below. Lets say that the input to the first inverter is 3.1 Volts, which is about as marginal a high signal as will be recognized as a high by the inverter. The output of the first inverter will be _____?? If we take that as the input to the second inverter the output of the second inverter will be ___ ?? Volts. Is it a solid high? The inverter supplies (+5 and ground) and the gain

drives unknown and marginal signals towards solid levels REP 01/26/20 ENGR224 VOH 5 ?? 3.1 4 VOUT 3 (Volts) 2 VOL |slope| = 1 1 0 1 2 VIL 3 VIH 4 VIN (Volts) 5 Input to inverter # 1 = 3.1V Page MOSFET 5.1-107 MOSFETs Solution to previous page VOH 5 0.65 3.1 5 4 VOUT

3 (Volts) 2 VOL 1 0 Output of 1 2 inverter # 1 VIL = 0.65V Input to INV #2 REP 01/26/20 ENGR224 |slope| = 1 3 VIH 4 VIN (Volts) 5 Input to inverter # 1 = 3.1V Page MOSFET 5.1-108 MOSFETs Propagation Delay and Rise and Fall Times of a signal vI VOH 90% of (VOH-VOL) Input Signal 50% 1/2(VOL+VOH) 10% of (VOH-VOL) VOL tr vO tf tPHL Time tPLH VOH Output Signal VOL tTHL REP 01/26/20 ENGR224

tTLH Time Page MOSFET 5.1-109 MOSFETs The Analog Switch The MOSFET is often used as a voltage-controlled switch. The voltage applied to the gate of each QN and QP turns them on and off. In the off position, the MOSFET behaves as an open circuit between drain and source In the on position, the MOSFET presents a resistance rDS between drain and source rDS 1 W k L ' n VGS Vt for small vDS More stringent requirements are placed on an analog switch, relative to a digital switch. When the switch is open, we want it to operate as an open circuit--the off-resistance switch should be very high (ideally infinite) A high on-resistance would result in signal attenuation The switch should be bidirectional (able to conduct in both directions) vA + - RL CL v O Analog Switch REP 01/26/20 ENGR224

Page MOSFET 5.1-110 MOSFETs Circuit Operation Notice that terminals are not labeled; they are interchangeable because the MOSFET is a symmetrical device. In general, the drain is the terminal which is at the higher voltage. v A 4V RL CL a v c v b 7V + - b RL CL REP 01/26/20 ENGR224 O O a + - v vC high; vA positive v A 4V

vC high; vA negative Page MOSFET 5.1-111 MOSFETs Equivalent Circuits for Transmission Gate v A (positive) RL a 5V + - b RL CL a b CL v v O + b b a a O 5V 5V + - + v A (negative) REP 01/26/20 ENGR224 Page MOSFET 5.1-112

5V MOSFETs CMOS Transmission Gate and Circuit Symbol Compared to the single NMOS switch, the transmission gate provides better performance at the expense of greater circuit complexity and chip area. C V DD C Output Input P Output Input N C (clock) REP 01/26/20 ENGR224 V C C Characteristics 0 1 Bidirectional open circuit Bidirectional short circuit SS Page MOSFET 5.1-113 MOSFETs MOSFET Internal Capacitances and High-Frequency Model The MOSFET has internal capacitances, however, they are neglected in the small-signal model. The gain of every MOSFET amplifier falls off at some high frequency. The MOSFET model must be augmented by including internal capacitances.

There are basically two types of internal capacitances in the MOSFET: The gate capacitive effect: the gate electrode (polysilicon) forms a parallel-plate capacitor with the channel, with the oxide layer serving as the capacitor dielectric. The source-body and drain-body depletion-layer capacitances: these are the capacitances of the reversed-biased pn junctions formed by the n + source region (source diffusion) and the p-type substrate, and by the n + drain region (drain diffusion) and the substrate. There will be five capacitances in total: Cgs, Cgd, Cgb, Csb, and Cdb, where the substrates indicate the location of the C gd capacitances in the model. G D v gs g m v gs C gs g mb vbs - ro C gb S v C sb bs Cdb B REP 01/26/20 ENGR224 Page MOSFET 5.1-114 MOSFETs The Gate Capacitive Effect The gate capacitive effect can be modeled by three capacitances C gs, Cgd, and Cgb. In the triode region at small vDS 1 C gs C gd WLCox 2

In saturation 2 C gs WLCox 3 C gd 0 In the cutoff region C gs C gd 0 C gb WLCox May be zero depending on the bulk potential Overlap capacitance Cov WLov Cox REP 01/26/20 ENGR224 Page MOSFET 5.1-115 MOSFETs The Junction Capacitances For source diffusion, the source-body capacitance, C sb Csb Csb 0 V 1 SB V0 Csb0 is the value of Csb at zero body bias VSB is the magnitude of the reverse-bias voltage V0 is the junction built-in voltage For drain diffusion, the drain-body capacitance, C db Cdb Cdb 0 V 1 DB V0 Cdb0 is the capacitance value at zero reverse-bias voltage VDB is the magnitude of the reverse-bias voltage V0 is the junction built-in voltage The above formulas assume small-signal operation. REP 01/26/20 ENGR224 Page MOSFET 5.1-116 MOSFETs The High-Frequency MOSFET Model C gd G D

v gs g m v gs C gs ro g mb vbs C gb S v C sb bs Cdb B C gd C gd G D v gs C gs - g m v gs G D ro Cdb

v gs C gs g m v gs S REP 01/26/20 ENGR224 S Page MOSFET 5.1-117 ro MOSFETs Unity-Gain Frequency (fT) The unity-gain frequency (fT) is defined as the frequency at which the short-circuit current-gain of the common-source configuration becomes unity. C gd Ii Io v gs C gs g m v gs ro - I o g mVgs sC gdVgs I o g mVgs Ii Vgs s C gs C gd Io gm I i s C gs C gd REP 01/26/20 ENGR224 The magnitude of the current gain becomes unity at the gm frequency

T T fT C gs C gd fT 2 gm 2 C gs C gd Page MOSFET 5.1-118

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