Program Technical Week

Program Technical Week

SCALING BEYOND 7NM: DESIGN-TECHNOLOGY CO-OPTIMIZATION AT THE RESCUE S. M. Y. SHERAZI & J. RYCKAERT WITH CONTRIBUTIONS FROM ALL INSITE TEAM ISPD 2016 INVITED TALK DESIGN-TECHNOLOGY CO-OPTIMIZATION AS PROCESS TECHNOLOGY PATHFINDER High-Mobility Gate-All-Around, Nanowires/ Channels Tunnel FETs -3 -2 -1 YOP (SiGe, Ge IIIV) DTCO EUV Technology options screening

Development Productio n Yield Ramp SAxP DSA DTCO mission - Down-select scaling scenarios - Define process assumptions sets and ground rules - Identify and verify key technology enablers for design 2 Metal 2 pitch 70 60 50 N16 193i LI LE3 cliff 80

EUV SE cliff 193i CPP SAQP cliff 90 193i CPP SADP cliff SCALING ROADMAP TO N7 AND BEYOND N10 90, 64 N7 40 193i Mx Mx LE3 LE3 cliff cliff 193i 193i Mx SADP cliff 64, 45 N5

30 45, 32 N3 EUV SE cliff 30, 24 20 193i Mx SAQP cliff 20, 18 10 10 20 30 40 50 60 70 80

Contacted Poly Pitch 3 90 100 Metal 2 pitch 70 60 50 N16 193i LI LE3 cliff 80 EUV SE cliff 193i CPP SAQP cliff 90 193i CPP SADP cliff SCALING ROADMAP TO N7 AND BEYOND

N10 90, 64 N7 193i Mx Mx LE3 LE3 cliff cliff 193i 193i Mx SADP cliff 64, 45 40 Metal 2 pitch around 32nmN5 30 N3 45, 32 EUV SE cliff 30, 24 20

193i Mx SAQP cliff CPP pitch around 42nm 20, 18 10 10 20 30 40 50 60 70 80 Contacted Poly Pitch 4 90 100 193i will be based on SAQP

90, 64 N10 1D metals only 60 EUV insertion in mix-match (vias/cuts) 50 N7 70 Metal 2 pitch N16 193i LI LE3 cliff 80 EUV SE cliff 193i CPP SAQP cliff 90 193i CPP SADP cliff SCALING ROADMAP TO N7 AND

BEYOND 193i Mx Mx LE3 LE3 cliff cliff 193i 193i Mx SADP cliff 64, 45 40 Metal 2 pitch around 32nmN5 30 N3 45, 32 SE cliff Designers need to help find EUV the 30, 24 193i Mx SAQP cliff 20 20, 18 CPP pitch around

42nm optimal patterning scheme 10 10 20 30 40 50 60 70 80 Contacted Poly Pitch 5 90 100 MANY ISSUES NEED TO BE RESOLVED AT DESIGN LEVEL Can I still achieve

area scaling with 1D How do I distribute power I How many routing tracks do I need to intercept? Can I still guarantee port accessibility Z How many fins per device do I need? E.g. what is the optimal track height How 1D interconnect impact the MOL scheme? 6 MANY ISSUES NEED TO BE

RESOLVED AT DESIGN LEVEL Can I still achieve area scaling with 1D How do I distribute power Can I still guarantee port accessibility Designers can define scaling paths that allow optimal area scaling 5 DTCO cases will be discussed: Z - OptimalI MOL patterning scheme - Fin depopulation - Optimal 1D routing scheme How many fins How many routing - Design rules simplification per device do I tracks do I need - New device architecture need? to intercept? Will 1D interconnect impact the MOL?

7 MANY ISSUES NEED TO BE RESOLVED AT DESIGN LEVEL Can I still achieve area scaling with 1D How do I distribute power Can I still guarantee port accessibility Designers can define scaling paths that allow optimal area scaling 5 DTCO cases will be discussed: Z - OptimalI MOL patterning scheme - Fin depopulation - Optimal 1D routing scheme How many fins How many routing - Design rules simplification per device do I tracks do I need - New device architecture need? to intercept?

Will 1D interconnect impact the MOL? 8 PARTIALLY SELF-ALIGNED MOL Via0 Via0 Via0 Gat e Gat e Active contact Spacer Gate Cap Active contact ILD0 Gate contac

t Gat e Gat e N10 used a partially self-aligned MOL All active contacts where patterned individually 9 PARTIALLY SELF-ALIGNED MOL REQUIRES 5 BLOCKS IN THE SRAM Using this scheme at a 42nm CPP and assuming an SADP + block patterning for active contacts M0A 42 BK2 BK3 BK1 BK0 46 BK4

Leads to 5 block masks to print the active contacts 10 FULLY SELF-ALIGNED MOL Gat e Via0 Via0 Gat e Active contact Spacer Gate Cap Active contact Via0 Gate contac

t Gat e Gat e ILD0 Now consecutive active contacts can be printed using one constructs thanks to the fully self-aligned scheme 11 FULLY SELF-ALIGNED MOL REDUCES THE MASK COUNT In this scheme 2 stitched direct LE prints can print the active contacts This solution enables a: - 2 color decomposition - 12 MANY ISSUES NEED TO BE RESOLVED AT DESIGN LEVEL Can I still achieve

area scaling with 1D How do I distribute power Can I still guarantee port accessibility Designers can define scaling paths that allow optimal area scaling 4 DTCO cases will be discussed: Z - OptimalI MOL patterning scheme - Fin depopulation - Optimal 1D routing scheme How many fins How many routing - Design rules simplification per device do I tracks do I need - New device architecture need? to intercept? Will 1D interconnect impact the MOL? 13

FIN DEPOPULATION ALLOWS AREA REDUCTION 9T = 4+4 active fins 7.5T = 3+3 active fins Fin depopulation relies on device performance improvement to reduce the standard cell template hence achieving area scaling 14 FIN DEPOPULATION REQUIRES FIN HEIGHT INCREASE Increasing fin height increases the effective width of the FET But improvement will depend heavily on 15 BALANCING CURRENTS MEANS BALANCING RESISTANCES Channel resistance reduction needs to balance source-drain parasitic increase 16

PROBLEM IS PARASITIC RESISTANCE INCREASES LARGELY AT N7 Increasing resistance is due to the low contact area at N7 At 7e-9 Ohm.cm2 the 3 fin device never matches the 4fin device 17 REDUCING CONTACT RESISTIVITY ALLOWS FIN DEPOPULATION Allowing a 7.5T standard cell to perform equally to a 9T standard cell, all pitches remaining constant. 18 MANY ISSUES NEED TO BE RESOLVED AT DESIGN LEVEL Can I still achieve area scaling with 1D How do I distribute power Can I still guarantee port accessibility

Designers can define scaling paths that allow optimal area scaling 4 DTCO cases will be discussed: Z - OptimalI MOL patterning scheme - Fin depopulation - Optimal 1D routing scheme How many fins How many routing - Design rules simplification per device do I tracks do I need - New device architecture need? to intercept? Will 1D interconnect impact the MOL? 19 WHAT YOU SEE IS NOT WHAT YOU GET Drawn... Proximity Rounding Narrowing

Pull back Expectation... Reality... Imec 10nm layout with LELELE M1 (64nm CPP 48nm MP) 20 DESIGNERS LAYOUT HAVE A LONG LIFE AFTER GDS-OUT Advanced patterning requires multiple patterning Decomposition may lead to very different patterns Should designers be aware of layout post-processing? Can EDA accommodate? 21 TRANSITION BETWEEN FEOL AND ROUTING LAYERS 1st Mx routing (M2) runs horizontal Gates run vertical Intermediate layers (e.g. MOL, M1) must provide:

Intra-cell routing Interface between FEOL and Mx 22 M1 VERTICAL IMPORTANT FOR PORT ACCESSIBILITY TO ROUTER - Complex MOL required to shift FEOL pins to M1 grid - Congested M2: all horizontal connections shifted to M2 23 CPP TO MX PITCH GEAR RATIO CREATED PATTERNING CONFLICTS Cells are placed on the CPP grid Resulting in M1 constructs out of grid 24 ADDING A LAYER UNDER VERTICAL M1: MINT Mint

- Optimal connectivity to FEOL and to routing layer - Limits M2 usage inside the cell - Requires introduction of extra layer 25 MINT REDUCES THE M1 COMPLEXITY M2 Without Mint: - Requires M2 to finish cells - Multiple M1 constructs VD D Mint power rail B ZN ZN VD

D A M2 VS S VD D B ZN ZN M2 VS S A VD D Example on a ND2D1 M2 Mint shift gate

connect Mint fly over gate for S/D With Mint - Limited M2 usage - Few M1 constructs - Optimal port access 26 M2 USAGE REDUCTION WITH MINT EXAMPLE ON AN XNOR2D1 9T version 7/7 tracks used 7.5T version 7.5T version With 5 DP Mint tracks With 7 QP Mint tracks 3/5 tracks used

0/5 tracks used 27 SCALING CELL HEIGHT USING BOOSTERS 6T version 7.5T version 6.5T version With 7 QP Mint tracks With 5 QP Mint tracks and Fully Self Aligned gate contact With 5 QP Mint tracks and Fully Self Aligned gate contact + Buried Power rail 0/5 tracks used 1/6.5 tracks Height

= used 1/6 tracks used Height = 240nm 208nm 6.5T = 6 T in number of poly used in the cells 28 Height = 192nm BURIED RAILS AND FULLY SELF ALIGNED GATE CONTACT (FP=24) Buried rail isolation VSS N gate Cell boundary

N-well N-fins VDD N gate P-N boundary W buried rail P gate Cell boundary P-fins Buried rail cap P gate P-Well P-substrate

18 POLY COUNT COMPARISON B/W 7.5T, AND 6T 384nm 480nm 20-Poly 30-Poly 378nm 630nm 7.5T DH Poly Count 6T with Buried PR + FSAG 6.5T with FSAG 7.5T 6.5T/6T < 7.5T 6.5T/6T = 7.5T 6.5T/6T > 7.5T 30 6T DH 61.2%

38.8% 0% MANY ISSUES NEED TO BE RESOLVED AT DESIGN LEVEL Can I still achieve area scaling with 1D How do I distribute power Can I still guarantee port accessibility Designers can define scaling paths that allow optimal area scaling 5 DTCO cases will be discussed: Z - OptimalI MOL patterning scheme - Fin depopulation - Optimal 1D routing scheme How many fins How many routing - Design rules simplification per device do I tracks do I need - New device architecture need?

to intercept? Will 1D interconnect impact the MOL? 31 Explosion of design rules because ... Designers dont know technology constraints... Technologists dont know what designers expect Need for simplification 32 WHATS LEFT ON THE TABLE AS LATEST NODE IS BEING ENABLED TEMPLATED DESIGN Dont ask for flexibility constrained by complex design rules Define a patterning friendly template Via spacing A T2T OUT

Via size VDD B Min metal area Via enclosure VSS Focus on key DFM rules 33 4 BASIC TEMPLATES ARE USED IN 7.5-TRACK STD-LEVEL A B C D S/D or gate Internal Vdd S/D gate S/D Internal Vss S/D or

gate This will ensure regular patterns at each layer 34 DESIGN AWARE MANUFACTURING Example: Litho-friendly place and route Poor Yield: Complex patterning scheme Metal density varied Better Yield: Simple patterning scheme Uniform Metal density Better Performance Lower power and higher perf. Poorer Performance Cap increase leading to power/performance drop 35 DESIGN AWARE MANUFACTURING Example: Litho-friendly place and route Modification of

cut/block process assumptions Better Yield: Patterning remains simple Little compromise on metal density Better Performance Minimize cap insertions for acceptable power/performance 36 MANY ISSUES NEED TO BE RESOLVED AT DESIGN LEVEL Can I still achieve area scaling with 1D How do I distribute power Can I still guarantee port accessibility Designers can define scaling paths that allow optimal area scaling 4 DTCOI cases will be discussed: Z - Optimal MOL patterning scheme - Fin depopulation - Optimal 1D routing scheme

How many fins How many routing per device do I - New device architecture tracks do I need need? to intercept? Will 1D interconnect impact the MOL? 37 Metal 2 pitch 70 60 50 N16 193i LI LE3 cliff 80 EUV SE cliff 193i CPP SAQP cliff 90

193i CPP SADP cliff SCALING ROADMAP TO N5 N10 90, 64 N7 40 193i Mx Mx LE3 LE3 cliff cliff 193i 193i Mx SADP cliff 64, 45 N5 Metal 2 pitch around 45, 32 N3 24nm 30 EUV SE cliff

30, 24 20 20, 18 193i Mx SAQP cliff CPP pitch around 30nm 10 10 20 30 40 50 60 70 80 Contacted Poly Pitch 38

90 100 VERTICAL FETS INTRODUCTION S G 3D view of an SRAM Cross-section D M1, M2 3D view of an SRAM with gate and nanowire TE Gate BE LG CGP 39 MOTIVATION W

Cu Source/Drain contact challenges!!! CGP Unit resistance [a.u.] 14000 Lg Unit resistance 12000 10000 8000 6000 4000 2000 0 5 10 15

20 25 30 Metal CD [nm] High density or small footprint device would be helpful in an increasingly high resistance interconnect 40 35 SRAM LAYOUTS: VERTICAL M1 HORIZONTAL M1 WL PD WL PG PD PG

area PU PG PU PD PU PG PU PD 41 AND CONCLUSION Scaling cannot only rely on lithography. Self-alignement techniques become key Design technology co-optimization is necessary to enable further technology scaling Solutions need to be tuned to design benchmarks such as standard cells and SRAMs Down the road, new device architectures

e.g. VFET must be considered THANK YOU ! 43

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