ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 5: September 8, 2014 Transistor Introduction (first order) Penn ESE370 Fall2014 -- DeHon

1 Today First order model There are always Rs and Cs Penn ESE370 Fall2014 -- DeHon 2

Previously Quasi-Static inputs transition, circuit responds, and settles Dynamic transition to roughly static states DC/Steady-State Ignore the capacitors Zeroth-order allows us to reason (mostly) at logic level about steady-state

functionality of typical gate circuits Penn ESE370 Fall2014 -- DeHon 3 Zero-th Order MOSFET Ideal Switch Vgs > Vth conducts Vgs < Vth does not conduct Vth threshold voltage

Gate draws no current from input Loads input capacitively Penn ESE370 Fall2014 -- DeHon 4 Zero-th Order MOSFET IDS

Penn ESE370 Fall2014 -- DeHon 5 First Order Model Switch Loads gate input capacitively Cg

Has finite drive strength Ron Penn ESE370 Fall2014 -- DeHon 6 Gate Output Assume this is equivalent circuit for gate output state

Penn ESE370 Fall2014 -- DeHon 7 Gate Output Load What is Vout if gate is unloaded? Penn ESE370 Fall2014 -- DeHon

8 Gate Output Load What happens to Vout when add a load? Penn ESE370 Fall2014 -- DeHon 9 Resistive Load

What happens when load is resistance? Penn ESE370 Fall2014 -- DeHon 10 Resistive Load If loaded resistively, and resistive load is too strong (resistance too low)

Cause output voltage to drop Penn ESE370 Fall2014 -- DeHon 11 Capacitive Load What happens when load is capacitance? Penn ESE370 Fall2014 -- DeHon

12 Capacitive Load Capacitive load does not change the steady-state output voltage Will effect the delay (settling time) Penn ESE370 Fall2014 -- DeHon

13 First Order Model Switch Loads gate input capacitively Draw no steady-state current Does not impact steady-state voltage Impacts Delay

Has finite drive strength Could form voltage divider with resistive load Impacts Delay Penn ESE370 Fall2014 -- DeHon 14 First Order Model (vs. Vds)

Penn ESE370 Fall2014 -- DeHon 15 First Order Model (vs. Vgs) Penn ESE370 Fall2014 -- DeHon 16

Refine to First Order Penn ESE370 Fall2014 -- DeHon 17 Zero-th Order Tells us how switches set (Vin=0) How are switches set in this case?

Penn ESE370 Fall2014 -- DeHon 18 Zero-th Order Tells us how switches set (Vin=0) V2=Vdd

Penn ESE370 Fall2014 -- DeHon Vout=0 19 Zero-th Order Tells us how switches set (Vin=0) V2=Vdd

Vout=0 Penn ESE370 Fall2014 -- DeHon 20 Zero-th Order Tells us how switches set (Vin=0) Leaves an RC Circuit we can analyze

ESE215 problem Penn ESE370 Fall2014 -- DeHon 21 Zero-th Order Tells us how switches set (Vin=0) Look at middle stage (V2) What is equivalent

circuit of load at V2? Penn ESE370 Fall2014 -- DeHon 22 Zero-th Order Tells us how switches set (Vin=0) Look at middle stage (V2) What is equivalent

output circuit for first pair of transistors driving V2? Penn ESE370 Fall2014 -- DeHon 23 Zero-th Order Tells us how switches set (Vin=0)

Look at middle stage (V2) What is relevant circuit? Penn ESE370 Fall2014 -- DeHon 24 Zero-th Order Tells us how switches set (Vin=0) Look at middle stage (V2)

Vdd Gnd Penn ESE370 Fall2014 -- DeHon What is relevant circuit? 25 Zero-th Order Tells us how

switches set (Vin=0) Look at middle stage (V2) What is delay of this stage? (charging V2 when Vin switch Vdd0) Penn ESE370 Fall2014 -- DeHon 26

What more does first-order model tell us? Delay Quasistatic behavior Voltage settling with resistive loads At least some basis for reasoning Penn ESE370 Fall2014 -- DeHon 27

What is this leaving out? Penn ESE370 Fall2014 -- DeHon 28 What is this leaving out? Penn ESE370 Fall2014 -- DeHon

29 What leaving out? What happens at intermediate voltages Not rail-to-rail (not just gnd or Vdd input) Details of dynamics, including Input not transition as step Intermediate drive strengths change with

Vgs Isnt really 0 current below threshold Penn ESE370 Fall2014 -- DeHon 30 Engineering Control Vth process engineer

Drive strength (Ron) circuit engineer control with sizing transistors Supply voltages (Vdd) range set by process detail use by circuit design Penn ESE370 Fall2014 -- DeHon 31

Engineering Control: Threshold Penn ESE370 Fall2014 -- DeHon 32 Engineering Control: Drive Strength

Penn ESE370 Fall2014 -- DeHon 33 Rs and Cs Penn ESE370 Fall2014 -- DeHon 34

Wire Capacitance Penn ESE370 Fall2014 -- DeHon 35 Wire Capacitance Penn ESE370 Fall2014 -- DeHon

A C r 0 d 36 Wire Resistance Penn ESE370 Fall2014 -- DeHon

37 Wire Resistance Penn ESE370 Fall2014 -- DeHon L R A

38 Wire Resistance Sanity check Wire twice as long = resistors in series Wire twice as wide = resistors in parallel Penn ESE370 Fall2014 -- DeHon L

R A 39 There are always Rs and Cs

Every wire (connection) has resistance Every wire has capacitance (Every wire has inductance) Modeling vs. discrete components Dominant effects Rbig + Rsmall Rbig (Rwire << Ron)? Cbig || Csmall Cbig (Cwire<>Cg)

Penn ESE370 Fall2014 -- DeHon 40 Big Ideas MOSFET Transistor as switch Purpose-driven simplified modeling Aid reasoning, sanity check, simplify design

Analysis methodology zero-th order to understand switch state (logic) First-order to get equivalent RC circuit (delay) New perspective on Rs and Cs Penn ESE370 Fall2014 -- DeHon 41 MOSFET

Penn ESE370 Fall2014 -- DeHon 42 Admin Normal Office Hours this week Ron on Monday 7pm (Detkin) Andre on Tuesday 4:155:30pm Ron on Wednesday 7pm (Detkin)

Lecture on Wed. Homework on Thursday Lab on Friday (Ketterer) Penn ESE370 Fall2014 -- DeHon 43