Task 1091.001: Highly Scalable Placement by Multilevel Optimization Task Leaders: Jason Cong (UCLA CS) and Tony Chan (UCLA Math) Students with Graduation Dates: Michalis Romesis (UCLA CS, March 2005 ---graduated) Kenton Sze (UCLA Math, July 2006 --- graduated) Min Xie (UCLA CS, September 2006 --- graduated) Guojie Luo (UCLA CS, September 2010) Research Staff: Joe Shinnerl, UCLA CS Industrial Liaisons Patrick McGuinness, Freescale Semiconductor, Inc. Natesan Venkateswaran, IBM Corporation Amit Chowdhary, Intel Corporation 20/1/30 UCLA VLSICAD LAB 2 Task Description and Anticipated Result Highly scalable multilevel, multiheuristic placement algorithms that address the critical placement needs of nanometer designs: scalability multi-constraint optimization --- timing, routability, power, manufacturability, etc. support of mixed-sized placement and incremental design. Quantitative study of the optimality and scalability of placement algorithms Construction of synthetic benchmarks with known optima to identify the
deficiencies of existing methods Our goal is to achieve one-process-generation benefit through innovation of physical-design technologies, especially placement. 20/1/30 UCLA VLSICAD LAB 3 Task Deliverables Report on new placement benchmarks with known optimal or near optimal solutions for all major objectives and constraints. Scalability and optimization studies on existing placement techniques (Completed 3-Nov-2003) Experiments and reports on the applicability of integrated AMG-based weighted aggregation and weighted interpolation. Improvement measured on both PEKO examples and industrial examples from SRC member companies ( Completed 1-Jun2004) Experiments and reports on multiheuristic, multilevel relaxation and the scalable incorporation of complex constraints into the enhanced multilevel framework. Improvement measured on both PEKO and industrial examples (Completed 1-Jun2005) A highly scalable placement tool that (i) supports multi-constraint optimization, mixed-sized placement, and incremental design and (ii) produces best-of-class results for both PEKO and industrial examples from SRC member companies (Completed 1-Jun-2006) Final report summarizing research accomplishments and future direction (PlannedOct-31, 2006) 20/1/30 UCLA VLSICAD LAB 4 Accomplishments in the Past Year
1. Improvements in mPL for routing density control [Best quality, ISPD 2006 contest] 2. Thermal-Driven Placement 3. Heterogeneous Placement 20/1/30 UCLA VLSICAD LAB 5 Relative Wirelength A Brief History of mPL mPL 1.0 [ICCAD00] UNIFORM CELL SIZE ESC Clustering Goto relaxation mPL 1.1 FC clustering Partitioning added to legalization mPL 2.0 RDFL relaxation Primal-dual netlist pruning mPL 3.0 [ICCAD03] QRS relaxation AMG interpolation Multiple V cycles NON-UNIFORM CELL SIZE 2000
20/1/30 2001 2002 mPL 5.0 mPL 4.0 Improved DP Backtracking V cycle 2003 2004 UCLA VLSICAD LAB Multilevel force directed Mixed-size capability mPL 6.0 Enhanced Routability handling 2005 2006 year 6 mPL: Generalized Force-Directed Placement Use of accurate objective functions [Bertsekas, 82, Naylor et al, 01] Optimization-based bin-density constraint formulation min
W ( x) s .t . ( x) , 1 1 where ( x ) d ( x ), c . Iterative Uzawa solver W ( x k 1 ) k ( x k ) ( k 1 ) ij ( k ) ij ( ij ) is a generalized force Multilevel for better runtime and wirelength 20/1/30 UCLA VLSICAD LAB 7 Accomplishments in the Past Year 1. Improvements in mPL for routing density control [Best quality, ISPD 2006 contest] 2. Thermal-Driven Placement 3. Heterogeneous Placement 20/1/30 UCLA VLSICAD LAB 8
Core Engine for Density Control Initial Finest Problem Final Placement coarsening One V cycle with comparable quality Minimum perturbation in the last stages of GFD interpolation coarsening Significant speed up without losing solution quality interpolation coarsening interpolation Coarsest Problem Overall scheme Routing density handling Residual density in each bin Even distribution of dummy density into bins Cell area inflation for better convergence GFD with Density Control Minimun perturbation 20/1/30 UCLA VLSICAD LAB 9
Macro Spreading Need area density below target value A1 w H [Nam, ISPD06] w2 Target distance between neighboring w1 W A2 fij macros A1 A2 w w1 w2 H : target density Spreading represented as objective n n min dxi dyi i 1 n fx ij fyij
i 1 i 1, j i dxi and dyi : perturbation 20/1/30 Hij x fxij and fyij : piece-wise linear function UCLA VLSICAD LAB 10 Experiment Results on ISPD06 mPL6 produces the best solution quality using ISPD06 routability-driven metric 20/1/30 UCLA VLSICAD LAB 11 Demonstration of mPL6 http://cadlab.cs.ucla.edu/cpmo/videos/mPL6-density.wmv 20/1/30 UCLA VLSICAD LAB 12 Accomplishments in the Past Year 1. Improvements in mPL core engine for mixed-size global placement 2. Thermal-Driven Placement 3. Heterogeneous Placement 20/1/30
UCLA VLSICAD LAB 13 Motivation High power density due to technology scaling Problems caused by high temperature Hot spots become more harmful Higher temperature Higher leakage power More heat Previously negligible effects become first-order effects Difficult estimation for power, timing, etc 20/1/30 UCLA VLSICAD LAB 14 Thermal Model P Cxy Cz Tj,1 Tj,4 Ti Tj,3 Tj,2 One layer mesh to model the substrate j (Ti - Tj) Cxy + (Ti Tsink) Cz = Pi
Cxy, Cz are the thermal conductance for the substrate and the heat sink Tsink Solved by Fast DCT Solve T from CT = P, given C and P Diagonalize C = T is the discrete cosine matrix is a diagonal matrix T = -1-1 P 20/1/30 UCLA VLSICAD LAB 15 Formulation & Solution minimize WL( x ) subject to i ( x) i ( x) (Nonoverlap) Ti ( x) ti ( x) Tdes (Temperatu re) Implement i(x) and ti(x) with filler cells and filler power without area Tdes is a given by user Solved by Uzawa Algorithm WL( x ( k 1) ) (i k ) i ( x ( k 1) ) i( k )Ti ( x ( k 1) ) 0 i i
(i k 1) (i k ) ( i ( x ( k 1) ) ) i( k 1) i( k ) (Ti ( x ( k 1) ) Tdes ) As additional thermal-aware GFD following a WL-driven V-Cycle 20/1/30 UCLA VLSICAD LAB 16 Experiment Results on IBM-FastPlace circuit T_even ibm01 ibm02 ibm03 ibm04 ibm05 ibm06 ibm07 ibm08 ibm09 ibm10 ibm11 ibm12 ibm13 ibm14 ibm15 ibm16 ibm17 ibm18 Average 60 60 60 60 60 60 60 60
60 60 60 60 60 60 60 60 60 60 20/1/30 Final Initial T WL T WL Qual impr WL incr 68.65 67.78 68.99 77.00 66.89 68.37 69.93 70.42 70.14 71.07 67.90 72.20 66.37 69.56
1.06 1.02 1.06 1.02 1.05 1.03 1.05 1.06 1.03 1.05 1.02 1.02 1.04 1.05 1.05 UCLA VLSICAD LAB Quality improvement (Tinit T final ) (Tinit Teven ) Teven is the ideal temperature with the same total power Max. on-chip temperature: Tinit after Step 1 Tfinal = Tdes after Step More than 90% quality improvement within 5% WL increase 17 Accomplishments in the Past Year 1. Improvements in mPL for routing density control [1st quality, ISPD 2006 contest] 2. Thermal-Driven Placement 3. Heterogeneous Placement
20/1/30 UCLA VLSICAD LAB 18 Motivation Need for placement on array type chips with pre-fabricated resources FPGA Structured ASIC Need for heterogeneous capability Memory, DSP, etc Block on sites of the same type 20/1/30 UCLA VLSICAD LAB 19 Related Work Academia VPR [Betz & Rose 97], PATH [Kong 02], SPCD [Chen & Cong 04,05], PPFF [Maidee et al, 03], CAPRI [Gopalakrishnan et al, 06] [ Most comparisons to out-dated tools No heterogeneous capability Industry Quartus II [Altera Corp.], ISE [Xilinx Inc.] Proprietary chips only Techniques not publicly documented 20/1/30
UCLA VLSICAD LAB 20 Heterogeneous Placement by mPL-H First analytical placer for heterogeneous placement Framework based on mPL6 [Chan et al, 05] Multiple layered placement DSP M-RAM One logical layer for each resource Forbidden regions blocked by obstacles LAB Uniform wirelength computation 20/1/30 Filler cells on each layer UCLA VLSICAD LAB 21 Demonstration of mPL-H http://cadlab.cs.ucla.edu/cpmo/videos/mPL-H.wmv 20/1/30
34% reduction in WL over 3 years One technology generation advancement UCLA VLSICAD LAB mPL6 WL runtime(s) 7.79E+07 2894 9.20E+07 2995 2.14E+08 9353 1.94E+08 8812 9.68E+07 3636 1.52E+08 10207 3.44E+08 13564 8.29E+08 30540 1.00 1.00 26 Technology Transfer in 2006 Discussions at conferences and workshops ASPDAC 2006, Yokohama, Japan ISPD 2006, San Jose, USA DAC 2006, San Francisco, USA Benchmark Releases (PEKO-MS) http://cadlab.cs.ucla.edu/~pubbench mPL release: http://cadlab.cs.ucla.edu/src_686_mpl/
20/1/30 UCLA VLSICAD LAB 27 Software Download Record PEKO/PEKU [2002 now] More than 360 downloads SRC member companies Cadence, IBM, Intel, Mentor Graphics,etc. NON-SRC member companies Synopsys, Magma, Monterey Design, etc. Universities CMU, Michigan, MIT, UC Berkeley, UCSD, etc., mPL [2001 now] More than 480 downloads SRC member companies Cadence, Intel, Mentor Graphics,etc. NON-SRC member companies Synopsys, Magma, Intrinsity, Oasys, etc. Universities
20/1/30 CMU, Michigan, Stanford, UCSD, Natl Taiwan U., etc., UCLA VLSICAD LAB 28 Publications in 2006 Conference papers ASPDAC 2006: J. Cong, M. Xie, A Robust Detailed Placement for Mixed-size IC Designs. ISPD 2006: T. F. Chan, J. Cong, J. Shinnerl, K. Sze and M. Xie, mPL6: Enhanced Multilevel Mixed-size Placement. Thesis Kenton Sze, Multilevel Optimization for VLSI Circuit Placement. Min Xie, Constraint-Driven Large Scale Circuit Placement Algorithms. 20/1/30 UCLA VLSICAD LAB 29 Room for Further Improvement? mPL4 20/1/30 mPL5 Swirls are difficult to correct with localized refinement UCLA VLSICAD LAB 30
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