CS151: Introduction and Five Components of a Computer
CS152 Computer Architecture and Engineering Lecture 1 Introduction and Five Components of a Computer CS152 / Spring 2002 Overvie w Intro to Computer Architecture (30 minutes) Administrative Matters (5 minutes) Course Style, Philosophy and Structure (15 min) Break (5 min) Organization and Anatomy of a Computer (25) min) Lec2.2 What is Computer Architecture Computer Architecture = Instruction Set Architecture + Machine Organization + .. Lec2.3 Instruction Set Architecture (subset of Computer Arch.) ... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and
functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. Amdahl, Blaaw, and Brooks, 1964 -- Organization of Programmable Storage SOFTWARE -- Data Types & Data Structures: Encodings & Representations -- Instruction Set -- Instruction Formats -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions Lec2.4 Computer Architectures Changing Definition 1950s to 1960s: Computer Architecture Course: Computer Arithmetic 1970s to mid 1980s: Computer Architecture Course: Instruction Set Design, especially ISA appropriate for compilers 1990s: Computer Architecture Course: Design of CPU, memory system, I/O system, Multiprocessors, Networks 2000s: Computer Architecture Course: Non VonNeumann architectures, Reconfiguration, Focused MIPs Lec2.5
The Instruction Set: a Critical Interface software instruction set hardware Lec2.6 Example ISAs (Instruction Set Architectures) Digital Alpha (v1, v3) 1992-97 HP PA-RISC (v1.1, v2.0) 1986-96 Sun Sparc (v8, v9) 1987-95
SGI MIPS (MIPS I, II, III, IV, V) 1986-96 Intel (8086,80286,80386, 80486,Pentium, MMX, ...) 1978-96 Lec2.7 MIPS R3000 Instruction Set Architecture (Summary) Registers Instruction Categories Load/Store Computational
Jump and Branch Floating Point - coprocessor R0 - R31 Memory Management Special PC HI LO 3 Instruction Formats: all 32 bits wide OP rs rt OP rs
rt OP rd sa funct immediate jump target Q: How many already familiar with MIPS ISA? Lec2.8 Organizatio n Capabilities & Performance Characteristics of Principal Functional Units (e.g., Registers, ALU, Shifters, Logic Units, ...) Logic Designer's View ISA Level FUs & Interconnect Ways in which these components
are interconnected Information flows between components Logic and means by which such information flow is controlled. Choreography of FUs to realize the ISA Register Transfer Level (RTL) Description Lec2.9 The Big Picture Since 1946 all computers have had 5 components Processor Input Control Memory Datapath Output Lec2.10 Example Organization TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20 MBus Module
SuperSPARC Floating-point Unit L2 $ Integer Unit Inst Cache Ref MMU Data Cache Store Buffer Bus Interface CC MBus L64852 MBus control M-S Adapter SBus SBus DMA
SBus Cards SCSI Ethernet DRAM Controller STDIO serial kbd mouse audio RTC Boot PROM Floppy Lec2.11 What is Computer Architecture? Application Operating System Compiler Firmware Instr. Set Proc. I/O system
Instruction Set Architecture Datapath & Control Digital Design Circuit Design Layout Coordination of many levels of abstraction Under a rapidly changing set of forces Design, Measurement, and Evaluation Lec2.12 Forces on Computer Architecture Technology Programming Languages Applications Computer Architecture Operating Systems Cleverness History
Lec2.13 Technolog y DRAM chip capacity Microprocessor Logic Density DRAM Size 1980 64 Kb 1983 256 Kb 1986 1 Mb 1989 4 Mb 1992 16 Mb
1996 64 Mb 1999 256 Mb 2002 1 Gb 10000000 R10000 P entium R4400 Tra nsistors Year 100000000 i80486 1000000 uP-Name i80386
i80286 100000 R3010 i8086 SU MIP S i80x86 M68K 10000 MIP S Alpha i4004 1000 1965 1970 1975 1980 1985 1990
1995 2000 2005 In ~1985 the single-chip processor (32-bit) and the single-board computer emerged => workstations, personal computers, multiprocessors have been riding this wave since In the 2002+ timeframe, these may well look like mainframes compared single-chip computer Lec2.14 (maybe 2 chips) Technology => dramatic change Processor logic capacity: about 30% per year clock rate: about 20% per year Memory DRAM capacity: about 60% per year (4x every 3 years) Memory speed: about 10% per year Cost per bit: improves about 25% per year Disk capacity: about 60% per year
Total use of data: 100% per 9 months! Network Bandwidth Bandwidth increasing more than 100% per year! Lec2.15 Performance Trends Log of Performance Supercomputers Mainframes Minicomputers Microprocessors Year 1970 1975 1980 1985 1990 1995
Lec2.16 Applications and Languages CAD, CAM, CAE, . . . Lotus, DOS, . . . Multimedia, . . . The Web, . . . JAVA, . . . The Net => ubiquitous computing ??? Lec2.17 Computers in the News: Sony Playstation 2000 (as reported in Microprocessor Report, Vol 13, No. 5) Emotion Engine: 6.2 GFLOPS, 75 million polygons per second Graphics Synthesizer: 2.4 Billion pixels per second Claim: Toy Story realism brought to games! Lec2.18 In p u t M u l t ip l i e r In p u t M u l t ip l i c a n d 32 M u l t i p l ic a n d
R e g is te r LoadM p 32=>34 s ig n E x <<1 32 34 34 32=>34 s ig n E x 1 0 3 4x2 M U X 34 34 M u lti x 2 / x 1 Arithmetic S u b /A d d
3 4 -b it A L U C o n tro l L o g ic 32 2 LoadHI L O r e g is te r ( 1 6 x 2 b it s ) 32 R e s u lt[H I] Prev 2 2 Booth Encoder H I r e g is t e r ( 1 6 x 2 b its )
LO Extra 2 bits 2 S h if tA ll LoadLO 32 "LO " 34 ClearHI Where are we going?? Single/multicycle Datapaths E N C [2 ] E N C [1 ] E N C [0 ] L O [1 :0 ]
32 R e s u lt [ L O ] 1000 CPU IFetchDcd WB Exec Mem Performance Processor-Memory Performance Gap: (grows 50% / year) 10 DRAM 9%/yr. DRAM (2X/10 yrs) 1 198 2 3 198 4 198 5
100 198 0 198 1 198 IFetchDcd CS152 Spring 99 Moores Law Proc 60%/yr. (2X/1.5yr) WB Time IFetchDcd Exec Mem IFetchDcd WB
Exec Mem WB Pipelining I/O Memory Systems Lec2.19 CS152: Course Content Computer Architecture and Engineering Instruction Set Design Computer Organization Interfaces Hardware Components Compiler/System View Logic Designers View Building Architect Construction Engineer Lec2.20
CS152: So what's in it for me? In-depth understanding of the inner-workings of modern computers, their evolution, and trade-offs present at the hardware/software boundary. Insight into fast/slow operations that are easy/hard to implementation hardware Out of order execution and branch prediction Experience with the design process in the context of a large complex (hardware) design. Functional Spec --> Control & Datapath --> Physical implementation Modern CAD tools Designer's "Conceptual" toolbox. Lec2.21 Conceptual tool box? Evaluation Techniques Levels of translation (e.g., Compilation) Levels of Interpretation (e.g., Microprogramming) Hierarchy (e.g, registers, cache, mem,disk,tape) Pipelining and Parallelism Static / Dynamic Scheduling Indirection and Address Translation Synchronous and Asynchronous Control Transfer Timing, Clocking, and Latching CAD Programs, Hardware Description Languages, Simulation
Physical Building Blocks (e.g., CLA) Understanding Technology Trends Lec2.22 Course Structure Design Intensive Class --- 75 to 150 hours per semester per student MIPS Instruction Set ---> Standard-Cell implementation Modern CAD System : Schematic capture and Simulation Design Description Computer-based "breadboard" Behavior over time Before construction Lectures (rough breakdown): Review: 2 weeks on ISA, arithmetic 1 1/2 weeks on technology, HDL, and arithmetic 3 1/2 weeks on standard Proc. Design and pipelining 2 weeks on DSP and Low Power Issues 2 weeks on memory and caches 1 1/2 weeks on Memory and I/O 2 weeks exams, presentations
Lec2.23 Typical Lecture Format 20-Minute Lecture 5- Minute Administrative Matters 25-Minute Lecture 5-Minute Break (water, stretch) 25-Minute Lecture Instructor will come to class early & stay after to answer questions Attention 20 min. Break 25 min. Break 25 min. In Conclusion, ... Time Lec2.24 Course Administration Instructor: Bob Brodersen ([email protected]) 402 Cory Hall Office Hours(Tentative): Mon 10:30-12:00 TAs: Ed Liao ([email protected]) Labs: UNIX accounts on Soda machines NT accounts in 119 Cory
Materials: http://bwrc.eecs.berkeley.edu/classes/cs152 Newsgroup: ucb.class.cs152 Text: Computer Organization and Design: The Hardware/Software Interface, Edition, Patterson and Hennessy Second Q: Need 2nd Edition? yes! >> 50% text changed, all exersizes changed all examples modernized, new sections, ... Lec2.25 Course Exams Reduce the pressure of taking exams Midterms: (approximately) March 5 and May 2 3 hrs to take 1.5-hr test (5:30-8:30 PM, 306 Soda). Our goal: test knowledge vs. speed writing Both mid-terms can bring summary sheets Lec2.26 Course Workload Reasonable workload (if you have good work habits) No final exam: Only 2 mid-terms Every lab feeds into the project Project teams have 4 or 5 members Spring 1995 HKN workload survey
(1 to 5, 5 being hardest) CS 150 CS 152 CS 162 4.2 3.4/3.5 3.9/4.0 CS 164 3.1 CS 169 3.6 CS 184 4.6 Spring 1997 HKN workload survey (1 to 5, 5 being hardest) CS 150 CS 152 CS 162 3.8 3.2 3.3 CS 164 4.0 CS 169 3.2 CS 184 3.3 Revised Science/Design units: now 3 Science, 2 Design Lec2.27 Homework Assignments and Project
Most assignment consists of two parts Individual Effort: Exercises from the text book Team Effort: Lab assignments First Homework: out Thursday on Website. Assignments (usually) go out on Tuesday Exercises due on a later Tuesday at beginning of lecture - Brief (15 minute) quiz on assignment material in lecture - Must understand assignment to do quiz - No late assignments! Labs reports due by midnight via submit program. Lab Homeworks returned in discussion section To spread computer workload put section time on them homeworks Discussion sections start next week 101 Tu 10:00 12:00 in 3109 Etcheverry 102 Th 4:00-6:00 in 343 Le Conte Turn in survey (On-line on Friday) Lec2.28 My Goal Show you how to understand modern computer architecture in its rapidly changing form. Show you how to design by leading you through the process on challenging design problems
Learn how to test things. NOT to talk at you so... ask questions come to office hours find me in the lab ... Lec2.29 Project/Lab Summary CAD tools will run on all NT workstations in Cory, but 119 Cory is primary CS152 lab. Get instructional UNIX account now (name account) Get card-key access to Cory now (3rd floor...) Lab assignments: Lab 1 Nothing to do! (1 week ) Lab 2 C -> MIPS, SPIM (2 weeks) Lab 3 Workview / Fast ALU Design (2 week) Lab 4 Single Cycle Processor Design (2 weeks) Lab 5 Pipelined Processor Design (2 weeks) Lab 6 Cache & DMA Design (3 weeks) Lab 7 Open ended work for final project
2-hour discussion section for later in term. Early sections may end in 1 hour. Make sure that you are free for both hours however! team in same section! Oral presentation and written report Lec2.30 Gradin g Grade breakdown Two Midterm Exams: Labs and Design Project: Homework and Quizzes: Project Group Participation Class Participation: 40% (combined) 40% 10% 5% 5% No late homeworks or labs: our goal grade, return in 1 week Grades posted on home page
Dont forget secret code on survey Written/email request for changes to grades CS Division guideline upper division class GPA between 2.7 and 3.1. average 152 grade will be a B or B+; set expectations accordingly Lec2.31 Course Problems Cant make midterm Tell us early and we will schedule alternate time Forgot to turn in homework/ Dog ate computer NO late homeworks or labs. What is cheating? Studying together in groups is encouraged Work must be your own Common examples of cheating: running out of time on a assignment and then pick up output, take homework from box and copy, person asks to borrow solution just to take a look, copying an exam question, ... Better off to skip assignment (homeworks: 5% of grade!) Labs worth more. However, each lab worth ~5% of grade. Doesnt help on quiz (15%of grade) anyway Lec2.32 Class decides on penalties for cheating; staff enforces Exercises (book): 0 for problem
0 for homework assignment subtract full value for assignment subtract 2X full value for assignment Labs leading to project (groups: only penalize individuals?) 0 for problem 0 for laboratory assignment subtract full value of laboratory subtract 2X full value of laboratory Exams 0 for problem 0 for exam Lec2.33 Project Simulates Industrial Environment Project teams have 4 or 5 members in same discussion section Must work in groups in the real world Communicate with colleagues (team members) Communication problems are natural What have you done? What answers you need from others? You must document your work!!! Everyone must keep an on-line notebook Communicate with supervisor (TAs) How is the teams plan?
Short progress reports are required: - What is the teams game plan? - What is each members responsibility? Lec2.34 Things We Hope You Will Learn from 152 Keep it simple and make it work Fully test everything individually and then together Retest everything whenever you make any changes Last minute changes are big no nos Group dynamics. Communication is the key to success: Be open with others of your expectations and your problems Everybody should be there on design meetings when key decisions are made and jobs are assigned Planning is very important: Promise what you can deliver; deliver more than you promise Murphys Law: things DO break at the last minute - Dont make your plan based on the best case scenarios -
Freeze your design and dont make last minute changes Never give up! It is not over until you give up. Lec2.35 What you should know from 61C, 150 Basic machine structure processor, memory, I/O Read and write basic C programs Read and write in an assembly language MIPS preferred Understand the steps in a make file and what they do compile, link, load & execute Understand the concept of virtual memory Logic design logical equations, schematic diagrams, FSMs, components Lec2.36 Getting into CS 152 Fill out survey it will be on-line by Friday Know the prerequisites CS 61C - assembly language and simple computer organization
CS 150 - Logic design. This prerequisite is changing. Still expect some knowledge of logic design and state machine design. No Pre-requisite Quiz but you better know the material! Have a look on the web site at past exams Lec2.37 Levels of Representation (61C Review) temp = v[k]; High Level Language Program v[k] = v[k+1]; v[k+1] = temp; Compiler lw$15, lw$16, sw sw Assembly Language Program Assembler Machine Language Program 0000 1010
0101 1100 0000 1010 1000 0110 1001 1111 Machine Interpretation Control Signal Specification ALUOP[0:3] <= InstReg[9:11] & MASK Lec2.38 Execution Cycle Instruction Obtain instruction from program storage Fetch Instruction Determine required actions and instruction size
Decode Operand Locate and obtain operand data Fetch Execute Result Compute result value or status Deposit results in storage for later use Store Next Instruction Determine successor instruction Lec2.39 Its all about communication Pentium III Chipset Proc Caches Busses Memory adapters
Controllers I/O Devices: Disks Displays Keyboards Networks All have interfaces & organizations Um. Its the network stupid???! Lec2.40 Summary All computers consist of five components Processor: (1) datapath and (2) control (3) Memory (4) Input devices and (5) Output devices Not all memory are created equally Cache: fast (expensive) memory are placed closer to the processor Main memory: less expensive memory--we can have more Interfaces are where the problems are - between functional units and between the computer and the outside world Need to design against constraints of performance, power, area and cost Lec2.41
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