Computer Architecture and Engineering Lecture 6: The Design ...

Computer Architecture and Engineering Lecture 6: The Design ...

CS152 Computer Architecture and Engineering Lecture 10 High-Level Design/ Microcode programming March 3, 2002 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/ 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Recap: Whats wrong with our CPI=1 processor? Arithmetic & Logical PC Inst Memory Reg File mux ALU mux setup Load PC Inst Memory ALU Data Mem Store PC mux Reg File

Critical Path Inst Memory Reg File ALU Data Mem Branch PC Inst Memory Reg File mux cmp mux setup mux Long Cycle Time All instructions take as much time as the slowest Real memory is not as nice as our idealized memory cannot always get the job done in one (short) cycle 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz 3/3/03 Operand Fetch Instruction Fetch PC

Next PC Exec UCB Spring 2003 Reg. File Result Store Data Mem Mem Access MemWr RegDst RegWr MemRd MemWr ALUctr ALUSrc ExtOp Equal nPC_sel Add registers between smallest steps Recap: Partitioning the CPI=1 Datapath CS152 / Kubiatowicz 3/3/03

ExtOp Equal B UCB Spring 2003 S Reg. File RegDst RegWr MemToReg MemRd MemWr ALUctr Ext ALUSrc ALU A Result Store Reg File Mem Access IR nPC_sel E Data Mem

Operand Fetch Instruction Fetch PC Next PC Recap: Example Multicycle Datapath M Critical Path ? CS152 / Kubiatowicz Recap: FSM specification instruction fetch IR <= MEM[PC] 0000 decode A <= R[rs] B <= R[rt] R-type S <= A fun B 0100 ORi S <= A or ZX 0110 LW S <= A + SX 1000

M <= MEM[S] 1001 SW BEQ S <= A + SX 1011 MEM[S] <= B PC <= PC + 4 1100 R[rd] <= S R[rt] <= S R[rt] <= M PC <= PC + 4 PC <= PC + 4 PC <= PC + 4 0101 3/3/03 0111 1010 UCB Spring 2003 PC <= Next(PC) 0011 Write-back Memory Execute 0001 CS152 / Kubiatowicz Recap: Micro-controller

Design The state digrams that arise define the controller for an instruction set processor are highly structured Use this structure to construct a simple microsequencer Each state in previous diagram becomes a microinstruction Microinstructions often taken sequentially Control reduces to programming this device sequencer control datapath control microinstruction () micro-PC 3/3/03 sequencer UCB Spring 2003 CS152 / Kubiatowicz Recap: Specific Sequencer from last lecture Sequencer-based control unit from last lecture Called microPC or PC vs. state register Control Value Effect 00 Next address = 0 01 Next address = dispatch ROM 10 Next address = address + 1 1 Adder ROM: 3/3/03 R-type BEQ

ori LW SW 000000 000100 001101 100011 101011 0100 0011 0110 1000 1011 UCB Spring 2003 Address Select Logic microPC Mux 2 1 0 0 ROM Opcode CS152 / Kubiatowicz Recap: Microprogram Control Specification PC Taken Next IR PC Ops Exec Mem Write-Back en sel A B Ex Sr ALU S R W M M-R Wr Dst 0000

0001 ? x inc 1 load 0011 0011 R: 0100 0101 ORi: 0110 0111 LW: 1000 1001 1010 SW: 1011 1100 0 1 x x x x x x x x x zero zero inc zero inc zero inc inc zero inc zero

BEQ 3/3/03 11 1 1 0 1 0 1 fun 1 1 0 0 1 1 0 0 or 1 1 0 0 1 0 1 0 add 1 1 0 1 1 0 1 1 0 1 0 add 1 1 0 UCB Spring 2003 0 1 0

CS152 / Kubiatowicz Representation Languages Hardware Representation Languages: Block Diagrams: FUs, Registers, & Dataflows Register Transfer Diagrams: Choice of busses to connect FUs, Regs Flowcharts Two different ways to describe sequencing & microoperations State Diagrams Fifth Representation "Language": Hardware Description Languages hw modules described like programs with i/o ports, internal state, & parallel execution of assignment statements E.G., ISP' VHDL Verilog Descriptions in these languages can be used as input to simulation systems "software breadboard" synthesis systems generate hw from high level description "To Design is to Represent" 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Simulation Before Construction "Physical Breadboarding" discrete components/lower scale integration preceeds actual construction of prototype verify initial design concept

No longer possible as designs reach higher levels of integration! Simulation Before Construction high level constructs implies faster to construct play "what if" more easily limited performance accuracy, however 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Levels of Description Architectural Simulation models programmer's view at a high level; written in your favorite programming language Functional/Behavioral/ Dataflow more detailed model, like the block diagram view Register Transfer commitment to datapath FUs, registers, busses; register xfer operations are clock phase accurate Logic model is in terms of logic gates; higher level MSI functions described in terms of these Circuit Less Abstract

More Accurate Slower Simulation electrical behavior; accurate waveforms Schematic capture + logic simulation package like Xilinx ISE Special languages + simulation systems for describing the inherent parallel activity in hardware 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Netl ist A key data structure (or representation) in the design process is the netlist: Network List A netlist lists components and connects them with nodes: ex: n1 n2 n3 n4 g1 n5 g3 g2 n6 g1 "and" n1 n2 n5 g2 "and" n3 n4 n6 g3 "or" n5 n6 n7

n7 Alternative format: n1 g1.in1 n2 g1.in2 n3 g2.in1 n4 g2.in2 n5 g1.out g3.in1 n6 g2.out g3.in2 n7 g3.out g1 "and" g2 "and" g3 "or" Netlist is what is needed for simulation and implementation. Could be at the transistor level, gate level, ... Could be hierarchical or flat. How do we generate a netlist? 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Des ign Flo w Design Entry Decoder(output x0,x1,x2,x3; inputs a,b) { wire abar, bbar; inv(bbar, b); inv(abar, a); nand(x0, abar, bbar); nand(x1, abar, b ); nand(x2, a,

bbar); nand(x3, a, b ); } High-level Analysis L o g ic B lo c k Technology Mapping la tc h s e t b y c o n f ig u r a t i o n b it- s t r e a m 1 IN P U T S 4 -L U T FF OUTPUT 0 4 - in p u t " lo o k u p t a b le " XilinxT Low-level Analysis 3/3/03 M UCB Spring 2003 CS152 / Kubiatowicz Des ign

Flo w Design Entry High-level Analysis Technology Mapping Circuit is described and represented: Graphically (Schematics) Textually (HDL) Other (Special Compilers) - Memories - Error Correcting Circuite Result of circuit specification (and compilation) is a netlist of: generic primitives - logic gates, flip-flops, or technology specific primitives LUTs/CLBs, transistors, discrete gates, or higher level library elements - adders, ALUs, register files, decoders, etc. Low-level Analysis 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Des ign Flo w Design Entry High-level

Analysis Technology Mapping High-level Analysis is used to verify: correct function rough: - timing - power - cost Common tools used are: simulator - check functional correctness, and static timing analyzer - estimates circuit delays based on timing model and delay parameters for library elements (or primitives). Low-level Analysis 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Des ign Flo w Design

Entry Technology Mapping: Converts netlist to implementation technology dependent details - Expands library elements, - Performs: partitioning, placement, routing High-level Analysis Low-level Analysis Technology Mapping Simulation and Analysis Tools perform lowlevel checks with: - accurate timing models, - wire delay For FPGAs this step could also use the actual device. Low-level Analysis 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Des ign Flo w

Design Entry High-level Analysis Netlist: used between and internally for all steps. Technology Mapping Low-level Analysis 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Des ign Schematics Entr are intuitive. They match our use of gate-level or block y diagrams. Somewhat physical. They imply a physical implementation. This is why we use them for datapaths Require a special tool (editor). Unless hierarchy is carefully designed, schematics can be confusing and difficult to follow. 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz High Level Design Languages (HDLs)

Basic Idea: Language constructs describe circuits with two basic forms: Structural descriptions similar to hierarchical netlist. Behavioral descriptions use higherlevel constructs (similar to conventional programming). Structural example: Decoder(output x0,x1,x2,x3; inputs a,b) { wire abar, bbar; inv(bbar, b); inv(abar, a); nand(x0, abar, bbar); nand(x1, abar, b ); nand(x2, a, bbar); nand(x3, a, b ); Originally designed to help in abstraction } and simulation. Behavioral example: Now logic synthesis tools exist to Decoder(output x0,x1,x2,x3; automatically convert from inputs a,b) behavioral descriptions to gate { netlist. case [a b] Greatly improves designer 00: [x0 x1 x2 x3] = 0x0; productivity. 01: [x0 x1 x2 x3] = 0x2; 10: [x0 x1 x2 x3] = 0x4;

However, this may lead you to falsely 11: [x0 x1 x2 x3] = 0x8; believe that hardware design can be endcase; reduced to writing programs! } CS152 / Kubiatowicz 3/3/03 UCB Spring 2003 Administratio n Midterm on Wednesday (3/12) from 5:30 - 8:30 No class on that day Pizza and Refreshments afterwards at LaVals on Euclid Ill Buy the pizza LaVals has an interesting history Review Session: Sunday (3/9), 7:00 PM in 306 Soda???? Lab 3 due this Thursday Make sure to come to section to talk with TAs Start forming groups 4 or 5 per group. Probably only 4 person groups unless there are problems Must come to section this Thursday to finalize groups 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Verilog History Originated at Automated Integrated Design Systems (renamed Gateway) in 1985. Acquired by Cadence in 1989.

Invented as simulation language. Synthesis was an afterthought. Many techniques for synthesis developed at Berkeley in 80s and applied commercially in the 90s. Around the same time as the origin of Verilog, the US Department of Defense developed VHDL. Because it was in the public domain it began to grow in popularity. VHDL is still popular within the government, in Europe and Japan, and some Universities. Standardization Afraid of losing market share, Cadence opened Verilog to the public in 1990. An IEEE working group was established in 1993, and ratified IEEE Standard 1394 (Verilog) in 1995. Verilog is language of choice of Silicon Valley companies, initially because of high-quality tool support and its similarity to C-language syntax. Most major CAD frameworks now support both VHDL and Verilog. 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Basic Example: 2-to1 mux in Structural Form //2-input multiplexor in gates module mux2 (in0, in1, select, out); input in0, in1, select; select output out; wire s0, w0, w1; out in0 not in1

(s0, select); and Notes: (w0, s0, in0), Comments start with // (w1, select, in1); or Input/output wires by default (out, w0, w1); module endmodule // mux2 port list declarations wire type primitive gates 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz 2-1 Mux in Dataflow Form //Dataflow description of mux module mux2 in0, in1, select, out); input in0,in1,select; output out; assign out = (~select & in0) | (select & in1); endmodule // mux2 Alternative: assign out = select ? in1 : in0; Notes: provides a way to describe combinational logic by its function rather than gate structure (similar to Boolean expressions). The assign keyword is used to indicate a continuous assignment. Whenever anything on the RHS changes the LHS is updated. 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz

2-to-1 mux Behavioral descriptionmodel of 2-to-1 // Behavioral in0 in1 out MUX // multiplexor. module mux2 (in0,in1,select,out); input in0,in1,select; output out; reg out; always @ (in0 or in1 or select) if (select) out=in1; else out=in0; endmodule // mux2 select Behavioral: use keyword always followed by one procedural statement Use Begin/End to place more statements after always @() specifier: wait until an event (here, change on one of 3 sigs) Output of procedural assignments must of of type reg a reg type retains its value until a new value is assigned Not necessarily a real register: only for @(posedge signal) 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Combining modules: Hierarchy & Bit //Assuming Vectors we have already

m2 in2 in3 m1 //4-input mux built from 3 2-input muxes module mux4 (in0, in1, in2, in3, select, out); input in0,in1,in2,in3; input [1:0] select; output out; wire w0,w1; in0 in1 m0 // defined a 2-input mux (either // structurally or behaviorally, out select[1] select[0] mux2 m0 (.select(select[0]), .in0(in0), .in1(in1), .out(w0)), m1 (.select(select[0]), .in0(in2), .in1(in3), .out(w1)), m2 (.select(select[1]), .in0(w0), .in1(w1), .out(out)); endmodule // mux4 Notes: Instance Names: m0, m1, m2 instantiation similar to primitives select is 2-bits wide

named port assignment 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Beh avio //4-input mux behavioral description ral mux4 (in0, in1, in2, in3, select, module 4-input in0,in1,in2,in3; input [1:0] select; to1 output out; mu reg out; xalways @ (in0 or in1 or in2 or in3 or out=in0; out=in1; out=in2; out=in3; select) Select in0 in1 in2 in3 2 MUX case (select) 2b00: 2b01: 2b10:

2b11: endcase endmodule // mux4 out); out Notes: Case construct equivalent to nested if constructs. Definition: A structural description is one where the function of the module is defined by the instantiation and interconnection of sub-modules. A behavioral description uses higher level language constructs and operators. Verilog allows modules to mix both behavioral constructs and sub-module instantiation. 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Beh //Behavioral avio model of 32-bit // wide 2-to-1 multiplexor. module ralmux32 (in0,in1,select,out); input [31:0] in0,in1; with input select; output [31:0] out; Bit reg [31:0] out; always @ (in0 or in1 or select) Vec if (select) out=in1; tors else out=in0; Select in0

MUX in1 32 32 out 32 endmodule // Mux Bit Vector Sizing and Ordering (32 bits, bit 31 MSB) A B 32 32 Adder //Behavioral model of 32-bit adder. module add32 (C,S,A,B); input [31:0] A,B; output [31:0] S; output C; reg [31:0] S; reg C; always @ (A or B) {C,S} = A + B; endmodule // Add 32 S C Concatenation Operation: {} 3/3/03

UCB Spring 2003 CS152 / Kubiatowicz Delay Specifications `timescale 1ns/1ps //Dataflow description of mux module mux2 in0, in1, select, out); input in0,in1,select; output out; assign out = #(5,10) select ? in1 : in0; endmodule // mux2 Notes: Delay specifications relative to timescale specification May be placed in many different syntactical positions #singlenumber - Delay specification for both edges #(rising,falling) - Delay specification for rising and falling edges 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Seq uen // Sequential Logic involves moduletial FF (CLK,Q,D); input D, CLK; Log output Q; reg Q; ic @ (posedge CLK) Q=D; always an edge Notes:

endmodule // FF //Parallel to Serial converter module ParToSer(LD, X, out, CLK); input [3:0] X; input LD, CLK; output out; reg out; reg [3:0] Q; assign out = Q[0]; always @ (posedge CLK) if (LD) Q=X; else Q = Q>>1; endmodule // mux2 3/3/03 always @ (posedge CLK) forces Q register to be rewritten every simulation cycle. >> operator does right shift (shifts in a zero on the left). Shifts on non-reg variables can be done with concatenation: wire [3:0] A, B; assign B = {1b0, A[3:1]} UCB Spring 2003 CS152 / Kubiatowicz Testing: Make sure that things work Testing methodologies Understand what correct behavior is when you design things - Collect vectors for later use Alewife Numbers Build monitor modules to check assertions of correct values Produce a regression test -

Set of tests to run each time something changes Types of test (Doug Clark): Directed Vectors test explicit behavior Random Vectors apply random values or orderings to device Daemons continuous error insertion Monitor modules: Check to see if invariants are maintained during long running simulations 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Monitor Modules: Passthrough testing module monitorsum32(carry,sum,A,B ); input [31:0] A,B; output [31:0] sum; output carry; reg [31:0] predsum; reg precarry; // The real adder sum32 mysum (carry,sum,A,B); `ifndef synthesis // This checker code only for simulation always @(A or B) begin #100 //wait for output to settle (dont make too long!) {predcarry,predsum} = A + B; if ((carry != predcarry) || (sum != predsum)) $display(>>> Mismatch: 0x%x+0x%x->0x%x carry %x, A,B,sum,carry); end `endif endmodule 3/3/03 UCB Spring 2003

CS152 / Kubiatowicz Testbench: Applying Directed Vectors module testmux; reg a, b, s; wire f; reg expected; // Unit under test. mux2 myMux (.select(s), .in0(a), .in1(b), .out(f)); initial begin s=0; a=0; b=1; expected=0; #10 a=1; b=0; expected=1; #10 s=1; a=0; b=1; expected=1; end initial $monitor( "select=%b in0=%b in1=%b out=%b, expected out=%b time=%d", s, a, b, f, expected, $time); endmodule // testmux Top-level modules written specifically to test sub-modules. Notes: initial block similar to always except only executes once (at beginning of simulation) #ns needed to advance time $monitor - prints output A variety of other system functions, similar to monitor exist for displaying output and controlling the simulation. CS152 / Kubiatowicz 3/3/03 UCB Spring 2003 Testbench: Randomized Vector Testing module testbench( ); reg [31:0] A,B; wire [31:0] sum; wire carry; reg [31:0] predsum; reg predcarry; Source of Vectors:

With $random->predicted result Actual vectors Check actual results against predicted // Device under test sum32 mysum (carry,sum,A,B); always begin A = $random; B = $random; #100 //wait for output to settle {predcarry,predsum} = A + B; if ((carry != predcarry) || (sum != predsum)) $display(>>> Mismatch: 0x%x+0x%x->0x%x carry %x, A,B,sum,carry); else $display(Successful: 0x%x+0x%x=0x%x carry %x, A,B,sum,carry); end endmodule 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Mor e The lecture notes only cover the very basics of Verilog and mostly just the Veri conceptual issues. log Hel The Mano textbook covers Verilog with many examples. p The Bhasker book is a good tutorial. On reserve in the Engineering

Complete language spec from the IEEE available on handouts page Synplify manual (for when we start using synthesis) 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Input Control Memory Datapath Output Todays Topics: Microprogramed control Administrivia Microprogram it yourself Exceptions 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Microprogramming (Maurice Wilkes) Control is the hard part of processor design Datapath is fairly regular and well-organized Memory is highly regular Control is irregular and global Microprogramming: -- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operations Microarchitecture: -- Logical structure and functional capabilities of the hardware as seen by the microprogrammer Historical Note: IBM 360 Series first to distinguish between architecture & organization

Same instruction set across wide range of implementations, each with different cost/performance 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Instruction Set Architecture (subset of Computer Arch.) ... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. Amdahl, Blaaw, and Brooks, 1964 -- Organization of Programmable Storage SOFTWARE -- Data Types & Data Structures: Encodings & Representations -- Instruction Set -- Instruction Formats -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Macroinstruction Interpretation Main Memory ADD SUB AND .

. . DATA execution unit CPU User program plus Data this can change! one of these is mapped into one of these AND microsequence control memory e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Variations on Microprogramming Horizontal Microcode control field for each control point in the machine seq addr A-mux B-mux bus enables register enables

Vertical Microcode compact microinstruction format for each class of microoperation local decode to generate all control points (remember ALU?) branch: seq-op add execute: ALU-op A,B,R memory: mem-op S, D Horizontal Vertical 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Extreme Horizontal 3 1 . . . N3 N2 N1 N0 1 bit for each loadable register enbMAR enbAC . . . input select Incr PC ALU control Depending on bus organization, many potential control combinations simply wrong, i.e., implies transfers that can never happen at the same time.

Makes sense to encode fields to save ROM space Example: mem_to_reg and ALU_to_reg should never happen simultaneously; => encode in single bit which is decoded rather than two separate bits NOTE: the encoding should be only wide enough so that parallel actions that the datapath supports should still be specifiable in a single microinstruction 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz More Vertical Format src dst D E C other control fields next states inputs D E C MUX Some of these may have nothing to do with registers! Multiformat Microcode: 6 1 3 0 cond 1 1

3 dst D E C 3/3/03 next address 3 src 3 alu Branch Jump Register Xfer Operation D E C UCB Spring 2003 CS152 / Kubiatowicz Hybrid Control Not all critical control information is derived from control logic E.g., Instruction Register (IR) contains useful control information, such as register sources, destinations, opcodes, etc. enable signals from control IR op to control 3/3/03 R S 1

R S 2 R D D E C D E C D E C rs1 rs2 Register File rd UCB Spring 2003 CS152 / Kubiatowicz Vax Microinstructions VAX Microarchitecture: 96 bit control store, 30 fields, 4096 instructions for VAX ISA encodes concurrently executable "microoperations" 95 87 84 USHF 001 = left

010 = right . . . 101 = left3 68 65 63 11 UALU USUB 010 = A-B-1 100 = A+B+1 UJMP 00 = Nop 01 = CALL 10 = RTN ALU Control 0 Jump Address Subroutine Control ALU Shifter Control Current intel architecture: 80-bit microcode, 8192 instructions 3/3/03 UCB Spring 2003

CS152 / Kubiatowicz Horizontal vs. Vertical Microprogramming NOTE: previous organization is not TRUE horizontal microprogramming; register decoders give flavor of encoded microoperations Most microprogramming-based controllers vary between: horizontal organization (1 control bit per control point) vertical organization (fields encoded in the control memory and must be decoded to control something) Horizontal Vertical + more control over the potential parallelism of operations in the datapath + easier to program, not very different from programming a RISC machine in assembly language - uses up lots of control store 3/3/03 - extra level of decoding may slow the machine down UCB Spring 2003 CS152 / Kubiatowicz How Effectively are we utilizing our hardware? IR <- Mem[PC] A <- R[rs]; B< R[rt]

S < A + B R[rd] < S; PC < PC+4; S < A or ZX R[rt] < S; PC < PC+4; S < A + SX S < A + SX M < Mem[S] Mem[S] <- B R[rd] < M; PC < PC+4; PC < PC+4; PC < PC+4; PC < PC+SX; Example: memory is used twice, at different times Ave mem access per inst = 1 + Flw + Fsw ~ 1.3 if CPI is 4.8, imem utilization = 1/4.8, dmem =0.3/4.8 We could reduce HW without hurting performance extra control 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Princeton Organization A-Bus B Bus next

PC P C IR ZX SX Reg File A B S Mem W-Bus Single memory for instruction and data access memory utilization -> 1.3/4.8 Sometimes, muxes replaced with tri-state buses Difference often depends on whether buses are internal to chip (muxes) or external (tri-state) In this case our state diagram does not change several additional control signals must ensure each bus is only driven by one source on each cycle 3/3/03 UCB Spring 2003 CS152 / Kubiatowicz Alternative datapath (book) Miminizes Hardware: 1 memory, 1 adder PCWr PCSrc RegDst ALUSelA

RegWr 32 PC 32 Rd busA A Reg File Rw busW busB 1 1 Mux 0 Imm 16 1 4 B << 2 Extend ExtOp 3/3/03 Rb 32 32 0 32

0 1 32 32 2 3 ALU Control 32 MemtoReg UCB Spring 2003 Zero ALU Out 32 5 Rt 0 Ra 32 ALU WrAdr 32 Din Dout 32 Rt Mux Ideal Memory

1 5 Mux RAdr 0 Rs Mem Data Reg 32 0 Mux 32 Instruction Reg 32 1 Mux PCWrCond Zero IorD MemWr IRWr ALUOp ALUSelB CS152 / Kubiatowicz Summary I Design Process Design Entry: Schematics, HDL, Compilers

High Level Analysis: Simulation, Testing, Assertions Technology Mapping: Turn design into physical implementation Low Level Analysis: Check out Timing, Setup/Hold, etc Verilog Three programming styles Structural: Like a Netlist - Instantiation of modules + wires between them Dataflow: Higher Level - Expressions instead of gates Behavioral: Hardware programming - Full flow-control mechanisms 3/3/03 - Registers, variables - File I/O, consol display, etc UCB Spring 2003 CS152 / Kubiatowicz Summary II Specialize state-diagrams easily captured by microsequencer simple increment & branch fields datapath control fields Most microprogramming-based controllers vary between: horizontal organization (1 control bit per control point) vertical organization (fields encoded in the control memory and must be decoded to control something) 3/3/03

UCB Spring 2003 CS152 / Kubiatowicz

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